Documentation of artyz7 registers

This document is a specification for the register interface of the FPGA module artyz7.

This file is automatically generated by hdl-registers version 8.0.2-dev. Code generator HtmlPageGenerator version 1.0.0. Generated 2025-09-17 20:53 from file regs_artyz7.toml at Git commit fd1631dfb1f7. Register hash b7fb508c65357996b25123c22f06694a7e051e5a.

Register modes

The following register modes are available.

Mode	Description
Read	Software can read a value that hardware provides.
Write	Software can write a value that is available for hardware usage.
Read, Write	Software can write a value and read it back. The written value is available for hardware usage.
Write-pulse	Software can write a value that is asserted for one clock cycle in hardware.
Read, Write-pulse	Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware.

Registers

The following registers make up the register list.

Name	Index	Address	Mode	Default value	Description
conf	0	0x0000	Read, Write	0x0	Configuration register.
command	1	0x0004	Write-pulse	0x0	When this register is written, all '1's in the written word will be asserted for one clock cycle in the FPGA logic.
status	2	0x0008	Read	0x0	Status register.
irq_status	3	0x000C	Read, Write-pulse	0x0	Reading a '1' in this register means the corresponding interrupt has triggered. Writing to this register will clear the interrupts where there is a '1' in the written word.
irq_mask	4	0x0010	Read, Write	0x0	A '1' in this register means that the corresponding interrupt is enabled.
build_id	5	0x0014	Read	0x0	Random build ID that can be used to distinguish between builds.
Register array resync, repeated 30 times. Iterator i ∈ [0, 29].
data	6 + i × 1	0x0018 + i × 0x0004	Read, Write-pulse	0x0
End register array resync.

Constants

The following constants are part of the register interface.

Name	Value	Description
expected_build_id	11311432	The build ID for this FPGA build. The value read from the build_id register shall be equal to this constant. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_project_name	"artyz7"	The name of the build project that executed the build of this FPGA. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_generics	"build_id=11311432, num_lanes=2"	The generic values that were set to the top level when building this FPGA. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_vivado_version	"2025.1"	The Vivado version that this FPGA was built with. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_git_commit	"fd1631dfb1f7"	The left-most characters of the git commit hash that this FPGA was built from. If there were local changes in the git repository, this will be noted in parenthesis. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_time	"2025-09-17 20:53:00"	A string describing at what time and date the FPGA was built. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_hostname	"runnervmf4ws1"	The hostname where this FPGA was built. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_operating_system	"Linux"	The operating that this FPGA was built on. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.
build_operating_system_info	"#18~24.04.1-Ubuntu SMP Sat Jun 28 04:46:03 UTC 2025 Linux-6.11.0-1018-azure-x86_64-with-glibc2.39"	More information about the operating system that this FPGA was built on. Note that this constant is added by a Python build hook. It is available in the FPGA build flow and the generated software code, but never in the simulation flow.