Coverage for tsfpga/create_ghdl_ls_config.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9import json 

10from pathlib import Path 

11 

12from tsfpga.system_utils import create_file, path_relative_to 

13 

14 

15def create_ghdl_ls_configuration(output_path, modules, vunit_proj, simlib=None): 

16 """ 

17 Create a configuration file (hdl-prj.json) for the vhdl-lsp VHDL Language Server 

18 (https://github.com/ghdl/ghdl-language-server). 

19 

20 Can be used with modules and an "empty" VUnit project, or with a complete VUnit 

21 project with all user files added. 

22 

23 Execution of this function takes roughly 12 ms for a large project (62 modules and a 

24 VUnit project). 

25 

26 Arguments: 

27 output_path (pathlib.Path): Output folder. 

28 modules: A list of Module objects. 

29 vunit_proj: A VUnit project. 

30 simlib (VivadoSimlibCommon): Source from this Vivado simlib project will be added. 

31 """ 

32 

33 def get_relative_path(path): 

34 return path_relative_to(path=path, other=output_path) 

35 

36 data = dict(options=dict(ghdl_analysis=[]), files=[]) 

37 

38 def add_compiled_library(path): 

39 relative_path = get_relative_path(path) 

40 data["options"]["ghdl_analysis"].append(f"-P{relative_path}") 

41 

42 data["options"]["ghdl_analysis"] += [ 

43 "--std=08", 

44 ] 

45 

46 # pylint: disable=protected-access 

47 compiled_vunit_libraries_path = Path(vunit_proj._output_path) / "ghdl" / "libraries" 

48 for compiled_library_path in compiled_vunit_libraries_path.glob("*"): 

49 add_compiled_library(compiled_library_path) 

50 

51 if simlib is not None: 

52 for library_name in simlib.library_names: 

53 add_compiled_library(simlib.output_path / library_name) 

54 

55 # The same file might be present in both module file list as well as VUnit project. 

56 # However the opposite might also be true in many cases. 

57 # E.g. files that depend on IP cores that are not included in the simulation project. 

58 # For this reason, add all files to a set first to avoid duplicates. 

59 files = set() 

60 

61 if modules is not None: 

62 for module in modules: 

63 for hdl_file in module.get_simulation_files(include_ip_cores=False): 

64 files.add(hdl_file.path) 

65 

66 for source_file in vunit_proj.get_compile_order(): 

67 files.add(Path(source_file.name).resolve()) 

68 

69 for file_path in files: 

70 data["files"].append(dict(file=str(get_relative_path(file_path)), language="vhdl")) 

71 

72 create_file(output_path / "hdl-prj.json", json.dumps(data))