Coverage for tsfpga/create_ghdl_ls_config.py: 0%

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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# Standard libraries 

10import json 

11from pathlib import Path 

12 

13# First party libraries 

14from tsfpga.system_utils import create_file, path_relative_to 

15 

16 

17def create_ghdl_ls_configuration(output_path, modules, vunit_proj, simlib=None): 

18 """ 

19 Create a configuration file (hdl-prj.json) for the vhdl-lsp VHDL Language Server 

20 (https://github.com/ghdl/ghdl-language-server). 

21 

22 Can be used with modules and an "empty" VUnit project, or with a complete VUnit 

23 project with all user files added. 

24 

25 Execution of this function takes roughly 12 ms for a large project (62 modules and a 

26 VUnit project). 

27 

28 Arguments: 

29 output_path (pathlib.Path): Output folder. 

30 modules: A list of Module objects. 

31 vunit_proj: A VUnit project. 

32 simlib (VivadoSimlibCommon): Source from this Vivado simlib project will be added. 

33 """ 

34 

35 def get_relative_path(path): 

36 return path_relative_to(path=path, other=output_path) 

37 

38 data = dict(options=dict(ghdl_analysis=[]), files=[]) 

39 

40 def add_compiled_library(path): 

41 relative_path = get_relative_path(path) 

42 data["options"]["ghdl_analysis"].append(f"-P{relative_path}") 

43 

44 data["options"]["ghdl_analysis"] += [ 

45 "--std=08", 

46 ] 

47 

48 # pylint: disable=protected-access 

49 compiled_vunit_libraries_path = Path(vunit_proj._output_path) / "ghdl" / "libraries" 

50 for compiled_library_path in compiled_vunit_libraries_path.glob("*"): 

51 add_compiled_library(compiled_library_path) 

52 

53 if simlib is not None: 

54 for library_name in simlib.library_names: 

55 add_compiled_library(simlib.output_path / library_name) 

56 

57 # The same file might be present in both module file list as well as VUnit project. 

58 # However the opposite might also be true in many cases. 

59 # E.g. files that depend on IP cores that are not included in the simulation project. 

60 # For this reason, add all files to a set first to avoid duplicates. 

61 files = set() 

62 

63 if modules is not None: 

64 for module in modules: 

65 for hdl_file in module.get_simulation_files(include_ip_cores=False): 

66 files.add(hdl_file.path) 

67 

68 for source_file in vunit_proj.get_compile_order(): 

69 files.add(Path(source_file.name).resolve()) 

70 

71 for file_path in files: 

72 data["files"].append(dict(file=str(get_relative_path(file_path)), language="vhdl")) 

73 

74 create_file(output_path / "hdl-prj.json", json.dumps(data))