Coverage for tsfpga/create_vhdl_ls_config.py: 0%

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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# Standard libraries 

10from pathlib import Path 

11 

12# Third party libraries 

13import tomlkit 

14 

15# First party libraries 

16from tsfpga.system_utils import create_file 

17from tsfpga.vivado.ip_cores import VivadoIpCores 

18 

19 

20def create_configuration( 

21 output_path, 

22 modules=None, 

23 vunit_proj=None, 

24 vivado_location=None, 

25 ip_core_vivado_project_directory=None, 

26): 

27 """ 

28 Create a configuration file (vhdl_ls.toml) for the rust_hdl VHDL Language Server. 

29 

30 Can be used with modules and an "empty" VUnit project, or with a complete VUnit 

31 project with all user files added. 

32 

33 Execution of this function takes roughly 12 ms for a large project (62 modules and a 

34 VUnit project). 

35 

36 Arguments: 

37 output_path (pathlib.Path): Output folder. 

38 modules: A list of Module objects. 

39 vunit_proj: A VUnit project. 

40 vivado_location (pathlib.Path): Vivado binary path. Will add unisim from this Vivado 

41 installation. 

42 ip_core_vivado_project_directory (pathlib.Path): Path to a Vivado project that contains 

43 generated "simulation" and "synthesis" files of IP cores 

44 (the "generate_target" TCL command). See simulate.py for an example of using this. 

45 """ 

46 toml_data = dict(libraries={}) 

47 

48 if modules is not None: 

49 for module in modules: 

50 vhd_file_wildcard = module.path.resolve() / "**" / "*.vhd" 

51 toml_data["libraries"][module.library_name] = dict(files=[str(vhd_file_wildcard)]) 

52 

53 if vunit_proj is not None: 

54 for source_file in vunit_proj.get_compile_order(): 

55 if source_file.library.name not in toml_data["libraries"]: 

56 toml_data["libraries"][source_file.library.name] = dict(files=[]) 

57 toml_data["libraries"][source_file.library.name]["files"].append( 

58 str(Path(source_file.name).resolve()) 

59 ) 

60 

61 if vivado_location is not None: 

62 vcomponents_package = ( 

63 vivado_location.parent.parent 

64 / "data" 

65 / "vhdl" 

66 / "src" 

67 / "unisims" 

68 / "unisim_retarget_VCOMP.vhd" 

69 ) 

70 if not vcomponents_package.exists(): 

71 raise FileNotFoundError(f"Could not find unisim file: {vcomponents_package}") 

72 

73 toml_data["libraries"]["unisim"] = dict(files=[str(vcomponents_package.resolve())]) 

74 

75 if ip_core_vivado_project_directory is not None: 

76 ip_core_vivado_project_directory = ip_core_vivado_project_directory.resolve() 

77 toml_data["libraries"]["xil_defaultlib"] = dict(files=[]) 

78 

79 # Vivado 2020.2+ (?) seems to place the files in "gen" 

80 ip_gen_dir = ( 

81 ip_core_vivado_project_directory / f"{VivadoIpCores.project_name}.gen" / "sources_1" 

82 ) 

83 if ip_gen_dir.exists(): 

84 vhd_file_wildcard = ip_gen_dir / "ip" / "**" / "*.vhd" 

85 toml_data["libraries"]["xil_defaultlib"]["files"].append(str(vhd_file_wildcard)) 

86 

87 create_file(output_path / "vhdl_ls.toml", tomlkit.dumps(toml_data))