Coverage for tsfpga/hdl_file.py: 100%
19 statements
« prev ^ index » next coverage.py v7.3.2, created at 2023-12-10 20:51 +0000
« prev ^ index » next coverage.py v7.3.2, created at 2023-12-10 20:51 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9# Standard libraries
10from pathlib import Path
13class HdlFile:
15 """
16 Class for representing a HDL source code file.
17 """
19 vhdl_file_ending = ".vhd"
20 verilog_source_file_ending = ".v"
21 verilog_header_file_ending = ".vh"
22 file_endings = (vhdl_file_ending, verilog_source_file_ending, verilog_header_file_ending)
24 def __init__(self, path: Path) -> None:
25 """
26 Arguments:
27 path: Path to a HDL source code file.
28 """
29 self.path = path
31 @property
32 def is_vhdl(self) -> bool:
33 """
34 True if the file is a VHDL file. Otherwise False.
35 """
36 return self.path.name.endswith(self.vhdl_file_ending)
38 @property
39 def is_verilog_source(self) -> bool:
40 """
41 True if the file is a Verilog source file. Otherwise False.
42 """
43 return self.path.name.endswith(self.verilog_source_file_ending)
45 @property
46 def is_verilog_header(self) -> bool:
47 """
48 True if the file is a Verilog header file. Otherwise False.
49 """
50 return self.path.name.endswith(self.verilog_header_file_ending)
52 def __str__(self) -> str:
53 return f"{self.__class__.__name__}('{self.path}')"