Coverage for tsfpga/test/test_vhdl_file_documentation.py: 100%

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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# First party libraries 

10from tsfpga.system_utils import create_file 

11from tsfpga.vhdl_file_documentation import VHDL_COMMENT_SEPARATOR, VhdlFileDocumentation 

12 

13 

14def test_documentation_header(tmp_path): 

15 data = f"""\ 

16{VHDL_COMMENT_SEPARATOR} 

17-- Copyright bla bla 

18{VHDL_COMMENT_SEPARATOR} 

19-- This is my documentation 

20-- 

21-- with 

22-- indentation 

23-- 

24-- And empty lines. 

25{VHDL_COMMENT_SEPARATOR} 

26 

27""" 

28 expected = """\ 

29This is my documentation 

30 

31 with 

32 indentation 

33 

34And empty lines. 

35""" 

36 

37 vhd_file = create_file(tmp_path / "file_for_test.vhd", data) 

38 assert VhdlFileDocumentation(vhd_file).get_header_rst() == expected 

39 

40 

41def test_only_copyright_header_should_return_no_documentation_header(tmp_path): 

42 data = f"""\ 

43{VHDL_COMMENT_SEPARATOR} 

44-- Copyright bla bla 

45{VHDL_COMMENT_SEPARATOR} 

46 

47""" 

48 

49 vhd_file = create_file(tmp_path / "file_for_test.vhd", data) 

50 assert VhdlFileDocumentation(vhd_file).get_header_rst() is None 

51 

52 

53def run_get_symbolator_component_test(tmp_path, vhdl_code, expected): 

54 vhd_file_path = create_file(tmp_path / "test_entity.vhd", vhdl_code) 

55 got = VhdlFileDocumentation(vhd_file_path).get_symbolator_component() 

56 

57 assert got == expected 

58 

59 

60def test_get_symbolator_component_simple(tmp_path): 

61 data = """ 

62entity test_entity is 

63 generic ( 

64 num_interfaces : positive 

65 ); 

66 port ( 

67 clk : in std_ulogic; 

68 --# {{}} 

69 input_ready : out std_ulogic := '0'; 

70 input_valid : in std_ulogic; 

71 --# {{}} 

72 output_ready : in std_ulogic_vector(0 to num_interfaces - 1); 

73 output_valid : out std_ulogic_vector(0 to num_interfaces - 1) := (others => '0') 

74 ); 

75end entity; 

76""" 

77 

78 # entity->component, no ranges, and no default values. 

79 expected = """\ 

80component test_entity is 

81 generic ( 

82 num_interfaces : positive 

83 ); 

84 port ( 

85 clk : in std_ulogic; 

86 --# {{}} 

87 input_ready : out std_ulogic; 

88 input_valid : in std_ulogic; 

89 --# {{}} 

90 output_ready : in std_ulogic_vector; 

91 output_valid : out std_ulogic_vector 

92 ); 

93end component;""" 

94 

95 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

96 

97 

98def test_get_symbolator_component_complex(tmp_path): 

99 data = """ 

100library common; 

101use common.addr_pkg.all; 

102 

103 

104entity test_entity is 

105 generic( 

106 buffer_segment_length_bytes : positive; 

107 dummy : positive := 10; 

108 -- comment 

109 silly : positive_vec_t(0 to 1) := 

110 -- comment again 

111 (others => 4) 

112 ) 

113 ;port( 

114 clk : in std_ulogic; 

115 --# {{}} 

116 request_ready : in std_ulogic := '0'; 

117 request_valid : out std_ulogic_vector(my_range_constant) := '0'; 

118 request_address : out addr_t(apa to hest) := (others => '0'); 

119 request_funky : out addr_t(apa to hest) := 

120 (others => '0'); 

121 request_slinky : out addr_t(apa to hest) := ( 

122 -- comment 

123 others => '0' 

124 ); 

125 --# {{}} 

126 release_last_address : in std_ulogic_vector(enables'range) 

127 := '0'; 

128 --# {{}} 

129 buffer_start_address : in addr_t(hest downto 0); 

130 buffer_last_address : in addr_t 

131 := (others => '0') 

132 ); 

133end entity; 

134 

135architecture a of test_entity is 

136 

137begin 

138 

139end architecture; 

140end; 

141end a; 

142""" 

143 

144 # entity->component, no ranges, and no default values. 

145 expected = """\ 

146component test_entity is 

147 generic ( 

148 buffer_segment_length_bytes : positive; 

149 dummy : positive; 

150 silly : positive_vec_t 

151 ); 

152 port ( 

153 clk : in std_ulogic; 

154 --# {{}} 

155 request_ready : in std_ulogic; 

156 request_valid : out std_ulogic_vector; 

157 request_address : out addr_t; 

158 request_funky : out addr_t; 

159 request_slinky : out addr_t; 

160 --# {{}} 

161 release_last_address : in std_ulogic_vector; 

162 --# {{}} 

163 buffer_start_address : in addr_t; 

164 buffer_last_address : in addr_t 

165 ); 

166end component;""" 

167 

168 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

169 

170 

171def test_get_symbolator_component_with_attributes(tmp_path): 

172 data = """ 

173entity test_entity is 

174 generic ( 

175 length_attribute : positive; 

176 attribute_length : positive 

177 ); 

178 port ( 

179 data_attribute : out std_ulogic_vector(my_range_constant) := '0'; 

180 attribute_data : out std_ulogic_vector(my_range_constant) := '0' 

181 ); 

182 

183 attribute apa : string; 

184 attribute apa of test_entity : entity is "hest"; 

185end entity; 

186""" 

187 

188 expected = """\ 

189component test_entity is 

190 generic ( 

191 length_attribute : positive; 

192 attribute_length : positive 

193 ); 

194 port ( 

195 data_attribute : out std_ulogic_vector; 

196 attribute_data : out std_ulogic_vector 

197 ); 

198end component;""" 

199 

200 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

201 

202 

203def test_get_symbolator_component_no_generics(tmp_path): 

204 data = """ 

205entity test_entity is 

206 port ( 

207 dummy_signal : out std_ulogic_vector(my_range_constant) := '0' 

208 ); 

209end entity; 

210""" 

211 

212 # entity->component, no ranges, and no default values. 

213 expected = """\ 

214component test_entity is 

215 port ( 

216 dummy_signal : out std_ulogic_vector 

217 ); 

218end component;""" 

219 

220 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

221 

222 

223def test_get_symbolator_component_last_port_no_newline(tmp_path): 

224 data = """ 

225entity test_entity is 

226 generic ( 

227 buffer_segment_length_bytes : positive_vec_t(0 to 1)); 

228 port ( 

229 dummy_signal : out std_ulogic_vector(my_range_constant) := '0');end entity; 

230""" 

231 

232 # entity->component, no ranges, and no default values. 

233 expected = """\ 

234component test_entity is 

235 generic ( 

236 buffer_segment_length_bytes : positive_vec_t 

237 ); 

238 port ( 

239 dummy_signal : out std_ulogic_vector 

240 ); 

241end component;""" 

242 

243 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

244 

245 

246def test_get_symbolator_component_last_port_parenthesis_on_same_line(tmp_path): 

247 data = """ 

248entity test_entity is 

249 generic ( 

250 buffer_segment_length_bytes : positive_vec_t(0 to 1) := (1, 2) ) 

251 ; 

252 port ( 

253 dummy_signal : out std_ulogic_vector(my_range_constant) := '0' ) 

254 ; 

255end entity; 

256""" 

257 

258 # entity->component, no ranges, and no default values. 

259 expected = """\ 

260component test_entity is 

261 generic ( 

262 buffer_segment_length_bytes : positive_vec_t 

263 ); 

264 port ( 

265 dummy_signal : out std_ulogic_vector 

266 ); 

267end component;""" 

268 

269 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

270 

271 

272def test_get_symbolator_component_with_comments(tmp_path): 

273 data = """ 

274entity test_entity is -- hello 

275 generic ( -- test ); end entity; -- Comment --in a -- comment 

276 apa : natural := 1-- ; 

277-- hest : natural 

278 ); 

279 port ( 

280 dummy : std_ulogic -- ); end entity; 

281 -- := 0 

282 ); 

283end entity; 

284""" 

285 

286 expected = """\ 

287component test_entity is 

288 generic ( 

289 apa : natural 

290 ); 

291 port ( 

292 dummy : std_ulogic 

293 ); 

294end component;""" 

295 

296 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

297 

298 

299def test_get_symbolator_component_with_separator_comments(tmp_path): 

300 data = """ 

301entity test_entity is 

302 port ( 

303 apa : out std_ulogic; -- trailing comment that shall be removed 

304 --# {{}} 

305 hest : out std_ulogic; 

306-- Out of place comment that shall be removed 

307-- foo : in std_ulogic; 

308 --# {{test 123}} 

309 zebra : out std_ulogic; 

310 ); 

311end entity; 

312""" 

313 

314 # entity->component, no ranges, and no default values. 

315 expected = """\ 

316component test_entity is 

317 port ( 

318 apa : out std_ulogic; 

319 --# {{}} 

320 hest : out std_ulogic; 

321 --# {{test 123}} 

322 zebra : out std_ulogic; 

323 ); 

324end component;""" 

325 

326 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

327 

328 

329def test_get_symbolator_component_with_complex_array_width(tmp_path): 

330 data = """ 

331entity test_entity is 

332 port ( 

333 dummy : out std_ulogic_vector( 

334 my_function( 

335 value=>generic_value 

336 ) - 1 

337 downto 0 

338 ) := (others => '0') 

339 ); 

340end entity; 

341""" 

342 

343 expected = """\ 

344component test_entity is 

345 port ( 

346 dummy : out std_ulogic_vector 

347 ); 

348end component;""" 

349 

350 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

351 

352 

353def run_get_symbolator_component_end_test(tmp_path, end_statement): 

354 data = f""" 

355entity test_entity is 

356 port ( 

357 clk : in std_ulogic; 

358 dummy_signal : out std_ulogic_vector(my_range_constant) := '0' 

359 ); 

360{end_statement}; 

361 

362architecture a of test_entity is 

363begin 

364 

365end architecture; 

366end; 

367end a; 

368""" 

369 

370 # entity->component, no ranges, and no default values. 

371 expected = """\ 

372component test_entity is 

373 port ( 

374 clk : in std_ulogic; 

375 dummy_signal : out std_ulogic_vector 

376 ); 

377end component;""" 

378 

379 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

380 

381 

382def run_get_symbolator_component_end_test_with_whitespace(tmp_path, end_statement): 

383 # As above but with lots of whitespace around the keywords. 

384 data = f""" 

385entity 

386 test_entity 

387 is 

388 

389 port ( 

390 clk : in std_ulogic; 

391 dummy_signal : out std_ulogic_vector(my_range_constant) := '0' 

392 ) 

393 ; 

394 

395 

396 {end_statement} 

397 ; 

398 

399architecture a of test_entity is 

400begin 

401 

402end architecture; 

403end; 

404end a; 

405""" 

406 

407 # entity->component, no ranges, and no default values. 

408 expected = """\ 

409component test_entity is 

410 port ( 

411 clk : in std_ulogic; 

412 dummy_signal : out std_ulogic_vector 

413 ); 

414end component;""" 

415 

416 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected) 

417 

418 

419def test_get_symbolator_component_end_only_keyword(tmp_path): 

420 end_statement = "end" 

421 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement) 

422 

423 

424def test_get_symbolator_component_no_end_entity_with_whitespace(tmp_path): 

425 end_statement = "end \n" 

426 run_get_symbolator_component_end_test_with_whitespace( 

427 tmp_path=tmp_path, end_statement=end_statement 

428 ) 

429 

430 

431def test_get_symbolator_component_end_name(tmp_path): 

432 end_statement = "end test_entity" 

433 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement) 

434 

435 

436def test_get_symbolator_component_end_name_with_whitespace(tmp_path): 

437 end_statement = "end \n test_entity \n" 

438 run_get_symbolator_component_end_test_with_whitespace( 

439 tmp_path=tmp_path, end_statement=end_statement 

440 ) 

441 

442 

443def test_get_symbolator_component_end_entity_name(tmp_path): 

444 end_statement = "end entity test_entity" 

445 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement) 

446 

447 

448def test_get_symbolator_component_end_entity_name_with_whitespace(tmp_path): 

449 end_statement = "end \n entity \n test_entity \n" 

450 run_get_symbolator_component_end_test_with_whitespace( 

451 tmp_path=tmp_path, end_statement=end_statement 

452 )