Coverage for tsfpga/vivado/test/test_logic_level_distribution_parser.py: 100%

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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9from tsfpga.vivado.logic_level_distribution_parser import LogicLevelDistributionParser 

10 

11 

12def test_get_table(): 

13 report = """ 

14 

151. Logic Level Distribution 

16--------------------------- 

17 

18+-----------------+-------------+-----+----+---+----+ 

19| End Point Clock | Requirement | 0 | 1 | 2 | 3 | 

20+-----------------+-------------+-----+----+---+----+ 

21| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 | 

22+-----------------+-------------+-----+----+---+----+ 

23* Columns represent the logic levels per end point clock 

24** Distribution is for top worst 1000 paths 

25""" 

26 expected = """\ 

27+-----------------+-------------+-----+----+---+----+ 

28| End Point Clock | Requirement | 0 | 1 | 2 | 3 | 

29+-----------------+-------------+-----+----+---+----+ 

30| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 | 

31+-----------------+-------------+-----+----+---+----+\ 

32""" 

33 assert LogicLevelDistributionParser.get_table(report) == expected 

34 

35 

36def test_get_maximum_logic_level(): 

37 table = """\ 

38+-----------------+-------------+-----+----+---+----+ 

39| End Point Clock | Requirement | 0 | 1 | 2 | 3 | 

40+-----------------+-------------+-----+----+---+----+ 

41| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 | 

42+-----------------+-------------+-----+----+---+----+\ 

43""" 

44 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 3 

45 

46 table = """\ 

47+-----------------+-------------+-----+----+---+----+ 

48| End Point Clock | Requirement | 0 | 1 | 2 | 7 | 

49+-----------------+-------------+-----+----+---+----+ 

50| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 | 

51+-----------------+-------------+-----+----+---+----+\ 

52""" 

53 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 7 

54 

55 table = """\ 

56+-----------------+-------------+-----+ 

57| End Point Clock | Requirement | 1 | 

58+-----------------+-------------+-----+ 

59| clk_fpga_0 | 2.000ns | 491 | 

60+-----------------+-------------+-----+ 

61""" 

62 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 1 

63 

64 

65def test_get_maximum_logic_level_no_paths(): 

66 table = """\ 

67+-----------------+-------------+ 

68| End Point Clock | Requirement | 

69+-----------------+-------------+\ 

70""" 

71 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 0