Coverage for tsfpga/test/unit/test_vhdl_file_documentation.py: 100%
17 statements
« prev ^ index » next coverage.py v6.4, created at 2022-05-28 04:01 +0000
« prev ^ index » next coverage.py v6.4, created at 2022-05-28 04:01 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project.
5# https://tsfpga.com
6# https://gitlab.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9from tsfpga.system_utils import create_file
11from tsfpga.vhdl_file_documentation import VhdlFileDocumentation, VHDL_COMMENT_SEPARATOR
14def test_documentation_header(tmp_path):
15 data = f"""\
16{VHDL_COMMENT_SEPARATOR}
17-- Copyright bla bla
18{VHDL_COMMENT_SEPARATOR}
19-- This is my documentation
20--
21-- with
22-- indentation
23--
24-- And empty lines.
25{VHDL_COMMENT_SEPARATOR}
27"""
28 expected = """\
29This is my documentation
31 with
32 indentation
34And empty lines.
35"""
37 vhd_file = create_file(tmp_path / "file_for_test.vhd", data)
38 assert VhdlFileDocumentation(vhd_file).get_header_rst() == expected
41def test_only_copyright_header_should_return_no_documentation_header(tmp_path):
42 data = f"""\
43{VHDL_COMMENT_SEPARATOR}
44-- Copyright bla bla
45{VHDL_COMMENT_SEPARATOR}
47"""
49 vhd_file = create_file(tmp_path / "file_for_test.vhd", data)
50 assert VhdlFileDocumentation(vhd_file).get_header_rst() is None
53def test_get_symbolator_component(tmp_path):
54 data = """
55library common;
56use common.addr_pkg.all;
59entity test_entity is
60 generic (
61 buffer_segment_length_bytes : positive
62 );
63 port (
64 clk : in std_logic;
65 --# {{}}
66 request_ready : in std_logic := '0';
67 request_valid : out std_logic_vector(my_range_constant) := '0';
68 request_address : out addr_t(apa to hest) := (others => '0');
69 request_funky : out addr_t(apa to hest) :=
70 (others => '0');
71 request_slinky : out addr_t(apa to hest)
72 := (others => '0');
73 --# {{}}
74 release_last_address : in std_logic_vector(enables'range) := '0';
75 --# {{}}
76 buffer_start_address : in addr_t(hest downto 0);
77 buffer_last_address : in addr_t := (others => '0')
78 );
79end entity;
81architecture a of test_entity is
83begin
84"""
86 # entity->component, no ranges, and no default values.
87 expected = """\
88component test_entity is
89 generic (
90 buffer_segment_length_bytes : positive
91 );
92 port (
93 clk : in std_logic;
94 --# {{}}
95 request_ready : in std_logic;
96 request_valid : out std_logic_vector;
97 request_address : out addr_t;
98 request_funky : out addr_t;
99 request_slinky : out addr_t;
100 --# {{}}
101 release_last_address : in std_logic_vector;
102 --# {{}}
103 buffer_start_address : in addr_t;
104 buffer_last_address : in addr_t
105 );
106end component;"""
108 vhd_file = create_file(tmp_path / "test_entity.vhd", data)
109 got = VhdlFileDocumentation(vhd_file).get_symbolator_component()
111 assert got == expected