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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 


4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 



10def get_slogan(): 

11 return ( 

12 "tsfpga is a development platform that aims to streamline all aspects of your FPGA project." 

13 ) 



16def get_short_doc(): 

17 return f"""{get_slogan()} 

18With its python build/simulation flow, along with complementary VHDL components, it is perfect \ 

19for CI/CD and test-driven development. 

20Focus has been placed on flexibility and modularization, achieving scalability even in very \ 

21large multi-vendor code bases. 




25def get_doc(): 

26 """ 

27 Prepend get_short_doc() to this to get the complete doc. 

28 """ 

29 return """Key features 



32* Source code centric project structure: Build projects, test configurations, constraints, \ 

33IP cores, etc. are handled close to the source code. 

34* Automatically adds build/simulation sources if a recognized folder structure is used. 

35* Enables local VUnit configuration setup without multiple ``run.py``. 

36* Handling of IP cores and simlib for your simulation project, with automatic re-compile when \ 


38* Python-based parallel Vivado build system. 

39* Register code generation from TOML: VHDL package, HTML documentation, C header, C++ class. 

40* VHDL AXI components that enable the register bus: AXI-to-AXI-Lite converter, \ 

41AXI-Lite interconnect, AXI-Lite mux (splitter), AXI-Lite clock domain crossing, AXI-Lite generic \ 

42register file. 


44The maintainers place high focus on quality, with everything having good unit test coverage and a \ 

45thought-out structure. 

46The project is mature and used in many production environments.