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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9from pathlib import Path 

10import tomlkit 

11 

12from tsfpga.system_utils import create_file 

13from tsfpga.vivado.ip_cores import VivadoIpCores 

14 

15 

16def create_configuration( 

17 output_path, 

18 modules=None, 

19 vunit_proj=None, 

20 vivado_location=None, 

21 ip_core_vivado_project_directory=None, 

22): 

23 """ 

24 Create a configuration file (vhdl_ls.toml) for the rust_hdl VHDL Language Server. 

25 

26 Can be used with modules and an "empty" VUnit project, or with a complete VUnit 

27 project with all user files added. 

28 

29 Execution of this function takes roughly 12 ms for a large project (62 modules and a 

30 VUnit project). 

31 

32 Arguments: 

33 output_path (`pathlib.Path`): Output folder. 

34 modules: A list of Module objects. 

35 vunit_proj: A VUnit project. 

36 vivado_location (`pathlib.Path`): Vivado binary path. Will add unisim from this Vivado 

37 installation. 

38 ip_core_vivado_project_directory (`pathlib.Path`): Path to a Vivado project that contains 

39 generated "simulation" and "synthesis" files of IP cores 

40 (the "generate_target" TCL command). See simulate.py for an example of using this. 

41 """ 

42 toml_data = dict(libraries={}) 

43 

44 if modules is not None: 

45 for module in modules: 

46 vhd_file_wildcard = module.path.resolve() / "**" / "*.vhd" 

47 toml_data["libraries"][module.library_name] = dict(files=[str(vhd_file_wildcard)]) 

48 

49 if vunit_proj is not None: 

50 for source_file in vunit_proj.get_compile_order(): 

51 if source_file.library.name not in toml_data["libraries"]: 

52 toml_data["libraries"][source_file.library.name] = dict(files=[]) 

53 toml_data["libraries"][source_file.library.name]["files"].append( 

54 str(Path(source_file.name).resolve()) 

55 ) 

56 

57 if vivado_location is not None: 

58 vcomponents_package = ( 

59 vivado_location.parent.parent 

60 / "data" 

61 / "vhdl" 

62 / "src" 

63 / "unisims" 

64 / "unisim_retarget_VCOMP.vhd" 

65 ) 

66 if not vcomponents_package.exists(): 

67 raise FileNotFoundError(f"Could not find unisim file: {vcomponents_package}") 

68 

69 toml_data["libraries"]["unisim"] = dict(files=[str(vcomponents_package.resolve())]) 

70 

71 if ip_core_vivado_project_directory is not None: 

72 ip_core_vivado_project_directory = ip_core_vivado_project_directory.resolve() 

73 toml_data["libraries"]["xil_defaultlib"] = dict(files=[]) 

74 

75 # Vivado 2020.2+ (?) seems to place the files in "gen" 

76 ip_gen_dir = ( 

77 ip_core_vivado_project_directory / f"{VivadoIpCores.project_name}.gen" / "sources_1" 

78 ) 

79 if ip_gen_dir.exists(): 

80 vhd_file_wildcard = ip_gen_dir / "ip" / "**" / "*.vhd" 

81 toml_data["libraries"]["xil_defaultlib"]["files"].append(str(vhd_file_wildcard)) 

82 

83 create_file(output_path / "vhdl_ls.toml", tomlkit.dumps(toml_data))