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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9 

10class HdlFile: 

11 

12 """ 

13 Class for representing a HDL source code file. 

14 """ 

15 

16 vhdl_file_ending = ".vhd" 

17 verilog_source_file_ending = ".v" 

18 verilog_header_file_ending = ".vh" 

19 file_endings = (vhdl_file_ending, verilog_source_file_ending, verilog_header_file_ending) 

20 

21 def __init__(self, path): 

22 """ 

23 Arguments: 

24 path (`pathlib.Path`): Path to a HDL source code file. 

25 """ 

26 self.path = path 

27 

28 @property 

29 def is_vhdl(self): 

30 """ 

31 True if the file is a VHDL file. Otherwise False. 

32 """ 

33 return self.path.name.endswith(self.vhdl_file_ending) 

34 

35 @property 

36 def is_verilog_source(self): 

37 """ 

38 True if the file is a Verilog source file. Otherwise False. 

39 """ 

40 return self.path.name.endswith(self.verilog_source_file_ending) 

41 

42 @property 

43 def is_verilog_header(self): 

44 """ 

45 True if the file is a Verilog header file. Otherwise False. 

46 """ 

47 return self.path.name.endswith(self.verilog_header_file_ending) 

48 

49 def __str__(self): 

50 return f"{self.__class__.__name__}('{self.path}')"