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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9""" 

10Some limited unit tests that check the generated code. 

11 

12It is also functionally tested in the file tb_artyz.vhd. 

13That testbench compiles the VHDL package and performs some run-time assertions on the 

14generated values. That test is considered more meaningful and exhaustive than a unit test would be. 

15""" 

16 

17import pytest 

18 

19import tsfpga 

20from tsfpga.system_utils import read_file 

21from tsfpga.registers.parser import from_toml 

22from tsfpga.registers.register_list import RegisterList 

23 

24 

25class RegisterConfiguration: 

26 def __init__(self, module_name, source_toml_file): 

27 self.register_list = from_toml(module_name, source_toml_file) 

28 self.register_list.add_constant("dummy_constant", "3") 

29 self.register_list.add_constant("flappy_constant", "91") 

30 

31 def test_vhdl_package(self, output_path, test_registers, test_constants): 

32 self.register_list.create_vhdl_package(output_path) 

33 vhdl = read_file(output_path / "artyz7_regs_pkg.vhd") 

34 

35 if test_registers: 

36 assert "constant artyz7_reg_map : " in vhdl, vhdl 

37 else: 

38 assert "constant artyz7_reg_map : " not in vhdl, vhdl 

39 

40 if test_constants: 

41 assert "constant artyz7_constant_dummy_constant : integer := 3;" in vhdl, vhdl 

42 else: 

43 assert "constant artyz7_constant_dummy_constant : integer := 3;" not in vhdl, vhdl 

44 

45 

46@pytest.fixture 

47def register_configuration(): 

48 return RegisterConfiguration( 

49 "artyz7", tsfpga.TSFPGA_EXAMPLE_MODULES / "artyz7" / "regs_artyz7.toml" 

50 ) 

51 

52 

53# False positive for pytest fixtures 

54# pylint: disable=redefined-outer-name 

55 

56 

57def test_vhdl_package_with_registers_and_constants(tmp_path, register_configuration): 

58 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=True) 

59 

60 

61def test_vhdl_package_with_registers_and_no_constants(tmp_path, register_configuration): 

62 register_configuration.register_list.constants = [] 

63 register_configuration.test_vhdl_package(tmp_path, test_registers=True, test_constants=False) 

64 

65 

66def test_vhdl_package_with_constants_and_no_registers(tmp_path, register_configuration): 

67 register_configuration.register_list.register_objects = [] 

68 register_configuration.test_vhdl_package(tmp_path, test_registers=False, test_constants=True) 

69 

70 

71def test_vhdl_package_with_only_one_register(tmp_path): 

72 """ 

73 Test that reg_map constant has valid VHDL syntax even when there is only one register. 

74 """ 

75 register_list = RegisterList(name="apa", source_definition_file=None) 

76 register_list.append_register(name="hest", mode="r", description="a single register") 

77 register_list.create_vhdl_package(tmp_path) 

78 vhdl = read_file(tmp_path / "apa_regs_pkg.vhd") 

79 

80 expected = """ 

81 constant apa_reg_map : reg_definition_vec_t(apa_reg_range) := ( 

82 0 => (idx => apa_hest, reg_type => r) 

83 ); 

84 

85 constant apa_regs_init : apa_regs_t := ( 

86 0 => std_logic_vector(to_signed(0, 32)) 

87 ); 

88""" 

89 assert expected in vhdl, vhdl