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1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project. 

5# https://tsfpga.com 

6# https://gitlab.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9from pathlib import Path 

10 

11from tsfpga.hdl_file import HdlFile 

12 

13 

14def test_file_type(): 

15 assert HdlFile(Path("file.vhd")).is_vhdl 

16 assert not HdlFile(Path("file.vhd")).is_verilog_source 

17 assert not HdlFile(Path("file.vhd")).is_verilog_header 

18 

19 assert HdlFile(Path("file.vh")).is_verilog_header 

20 assert HdlFile(Path("file.v")).is_verilog_source 

21 

22 

23def test_can_cast_to_string_without_error(): 

24 str(HdlFile(Path("file.vhd")))