Coverage for tsfpga/create_vhdl_ls_config.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# Standard libraries 

10from pathlib import Path 

11from typing import TYPE_CHECKING, Any, Optional 

12 

13# Third party libraries 

14import rtoml 

15 

16# First party libraries 

17from tsfpga.vivado.ip_cores import VivadoIpCores 

18 

19if TYPE_CHECKING: 

20 # Local folder libraries 

21 from .module_list import ModuleList 

22 

23 

24def create_configuration( 

25 output_path: Path, 

26 modules: Optional["ModuleList"] = None, 

27 vunit_proj: Optional[Any] = None, 

28 vivado_location: Optional[Path] = None, 

29 ip_core_vivado_project_directory: Optional[Path] = None, 

30) -> None: 

31 """ 

32 Create a configuration file (vhdl_ls.toml) for the rust_hdl VHDL Language Server. 

33 

34 Can be used with modules and an "empty" VUnit project, or with a complete VUnit 

35 project with all user files added. 

36 

37 Execution of this function takes roughly 12 ms for a large project (62 modules and a 

38 VUnit project). 

39 

40 Arguments: 

41 output_path: vhdl_ls.toml file will be placed in this folder. 

42 modules: A list of Module objects. 

43 vunit_proj: A VUnit project. 

44 vivado_location: Vivado binary path. Will add unisim from this Vivado installation. 

45 ip_core_vivado_project_directory: Path to a Vivado project that contains 

46 generated "simulation" and "synthesis" files of IP cores 

47 (the "generate_target" TCL command). See simulate.py for an example of using this. 

48 """ 

49 toml_data: dict[str, dict[str, dict[str, list[str]]]] = dict(libraries={}) 

50 

51 if modules is not None: 

52 for module in modules: 

53 vhd_file_wildcard = module.path.resolve() / "**" / "*.vhd" 

54 toml_data["libraries"][module.library_name] = dict(files=[str(vhd_file_wildcard)]) 

55 

56 if vunit_proj is not None: 

57 for source_file in vunit_proj.get_compile_order(): 

58 if source_file.library.name not in toml_data["libraries"]: 

59 toml_data["libraries"][source_file.library.name] = dict(files=[]) 

60 toml_data["libraries"][source_file.library.name]["files"].append( 

61 str(Path(source_file.name).resolve()) 

62 ) 

63 

64 if vivado_location is not None: 

65 vcomponents_package = ( 

66 vivado_location.parent.parent 

67 / "data" 

68 / "vhdl" 

69 / "src" 

70 / "unisims" 

71 / "unisim_retarget_VCOMP.vhd" 

72 ) 

73 if not vcomponents_package.exists(): 

74 raise FileNotFoundError(f"Could not find unisim file: {vcomponents_package}") 

75 

76 toml_data["libraries"]["unisim"] = dict(files=[str(vcomponents_package.resolve())]) 

77 

78 if ip_core_vivado_project_directory is not None: 

79 ip_core_vivado_project_directory = ip_core_vivado_project_directory.resolve() 

80 toml_data["libraries"]["xil_defaultlib"] = dict(files=[]) 

81 

82 # Vivado 2020.2+ (?) seems to place the files in "gen" 

83 ip_gen_dir = ( 

84 ip_core_vivado_project_directory / f"{VivadoIpCores.project_name}.gen" / "sources_1" 

85 ) 

86 if ip_gen_dir.exists(): 

87 vhd_file_wildcard = ip_gen_dir / "ip" / "**" / "*.vhd" 

88 toml_data["libraries"]["xil_defaultlib"]["files"].append(str(vhd_file_wildcard)) 

89 

90 rtoml.dump(obj=toml_data, file=output_path / "vhdl_ls.toml", pretty=True)