Coverage for tsfpga/test/test_hdl_file.py: 100%
19 statements
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1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9from pathlib import Path
11import pytest
13from tsfpga.hdl_file import HdlFile
16def test_file_endings():
17 assert HdlFile.file_endings == (
18 ".vhd",
19 ".vhdl",
20 ".vho",
21 ".v",
22 ".vp",
23 ".vo",
24 ".vh",
25 ".sv",
26 ".svp",
27 ".svh",
28 )
31def test_file_type():
32 assert HdlFile(Path("file.vhd")).type == HdlFile.Type.VHDL
33 assert HdlFile(Path("FILE.VHDL")).type == HdlFile.Type.VHDL
35 assert HdlFile(Path("file.v")).type == HdlFile.Type.VERILOG_SOURCE
36 assert HdlFile(Path("file.vh")).type == HdlFile.Type.VERILOG_HEADER
38 assert HdlFile(Path("file.sv")).type == HdlFile.Type.SYSTEMVERILOG_SOURCE
39 assert HdlFile(Path("FILE.SVP")).type == HdlFile.Type.SYSTEMVERILOG_SOURCE
40 assert HdlFile(Path("file.svh")).type == HdlFile.Type.SYSTEMVERILOG_HEADER
43def test_unknown_file_ending_raises_exception():
44 with pytest.raises(ValueError) as exception_info:
45 HdlFile(Path("file.unknown"))
46 assert str(exception_info.value) == "Unsupported HDL file ending: file.unknown"
49def test_can_cast_to_string_without_error():
50 str(HdlFile(Path("file.vhd")))