Coverage for tsfpga/test/test_vhdl_file_documentation.py: 100%
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1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9from tsfpga.system_utils import create_file
10from tsfpga.vhdl_file_documentation import VHDL_COMMENT_SEPARATOR, VhdlFileDocumentation
13def test_documentation_header(tmp_path):
14 data = f"""\
15{VHDL_COMMENT_SEPARATOR}
16-- Copyright bla bla
17{VHDL_COMMENT_SEPARATOR}
18-- This is my documentation
19--
20-- with
21-- indentation
22--
23-- And empty lines.
24{VHDL_COMMENT_SEPARATOR}
26"""
27 expected = """\
28This is my documentation
30 with
31 indentation
33And empty lines.
34"""
36 vhd_file = create_file(tmp_path / "file_for_test.vhd", data)
37 assert VhdlFileDocumentation(vhd_file).get_header_rst() == expected
40def test_only_copyright_header_should_return_no_documentation_header(tmp_path):
41 data = f"""\
42{VHDL_COMMENT_SEPARATOR}
43-- Copyright bla bla
44{VHDL_COMMENT_SEPARATOR}
46"""
48 vhd_file = create_file(tmp_path / "file_for_test.vhd", data)
49 assert VhdlFileDocumentation(vhd_file).get_header_rst() is None
52def run_get_symbolator_component_test(tmp_path, vhdl_code, expected):
53 vhd_file_path = create_file(tmp_path / "test_entity.vhd", vhdl_code)
54 got = VhdlFileDocumentation(vhd_file_path).get_symbolator_component()
56 assert got == expected
59def test_get_symbolator_component_simple(tmp_path):
60 data = """
61entity test_entity is
62 generic (
63 num_interfaces : positive
64 );
65 port (
66 clk : in std_ulogic;
67 --# {{}}
68 input_ready : out std_ulogic := '0';
69 input_valid : in std_ulogic;
70 --# {{}}
71 output_ready : in std_ulogic_vector(0 to num_interfaces - 1);
72 output_valid : out std_ulogic_vector(0 to num_interfaces - 1) := (others => '0')
73 );
74end entity;
75"""
77 # entity->component, no ranges, and no default values.
78 expected = """\
79component test_entity is
80 generic (
81 num_interfaces : positive
82 );
83 port (
84 clk : in std_ulogic;
85 --# {{}}
86 input_ready : out std_ulogic;
87 input_valid : in std_ulogic;
88 --# {{}}
89 output_ready : in std_ulogic_vector;
90 output_valid : out std_ulogic_vector
91 );
92end component;"""
94 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
97def test_get_symbolator_component_complex(tmp_path):
98 data = """
99library common;
100use common.addr_pkg.all;
103entity test_entity is
104 generic(
105 buffer_segment_length_bytes : positive;
106 dummy : positive := 10;
107 -- comment
108 silly : positive_vec_t(0 to 1) :=
109 -- comment again
110 (others => 4)
111 )
112 ;port(
113 clk : in std_ulogic;
114 --# {{}}
115 request_ready : in std_ulogic := '0';
116 request_valid : out std_ulogic_vector(my_range_constant) := '0';
117 request_address : out addr_t(apa to hest) := (others => '0');
118 request_funky : out addr_t(apa to hest) :=
119 (others => '0');
120 request_slinky : out addr_t(apa to hest) := (
121 -- comment
122 others => '0'
123 );
124 --# {{}}
125 release_last_address : in std_ulogic_vector(enables'range)
126 := '0';
127 --# {{}}
128 buffer_start_address : in addr_t(hest downto 0);
129 buffer_last_address : in addr_t
130 := (others => '0')
131 );
132end entity;
134architecture a of test_entity is
136begin
138end architecture;
139end;
140end a;
141"""
143 # entity->component, no ranges, and no default values.
144 expected = """\
145component test_entity is
146 generic (
147 buffer_segment_length_bytes : positive;
148 dummy : positive;
149 silly : positive_vec_t
150 );
151 port (
152 clk : in std_ulogic;
153 --# {{}}
154 request_ready : in std_ulogic;
155 request_valid : out std_ulogic_vector;
156 request_address : out addr_t;
157 request_funky : out addr_t;
158 request_slinky : out addr_t;
159 --# {{}}
160 release_last_address : in std_ulogic_vector;
161 --# {{}}
162 buffer_start_address : in addr_t;
163 buffer_last_address : in addr_t
164 );
165end component;"""
167 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
170def test_get_symbolator_component_with_attributes(tmp_path):
171 data = """
172entity test_entity is
173 generic (
174 length_attribute : positive;
175 attribute_length : positive
176 );
177 port (
178 data_attribute : out std_ulogic_vector(my_range_constant) := '0';
179 attribute_data : out std_ulogic_vector(my_range_constant) := '0'
180 );
182 attribute apa : string;
183 attribute apa of test_entity : entity is "hest";
184end entity;
185"""
187 expected = """\
188component test_entity is
189 generic (
190 length_attribute : positive;
191 attribute_length : positive
192 );
193 port (
194 data_attribute : out std_ulogic_vector;
195 attribute_data : out std_ulogic_vector
196 );
197end component;"""
199 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
202def test_get_symbolator_component_no_generics(tmp_path):
203 data = """
204entity test_entity is
205 port (
206 dummy_signal : out std_ulogic_vector(my_range_constant) := '0'
207 );
208end entity;
209"""
211 # entity->component, no ranges, and no default values.
212 expected = """\
213component test_entity is
214 port (
215 dummy_signal : out std_ulogic_vector
216 );
217end component;"""
219 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
222def test_get_symbolator_component_last_port_no_newline(tmp_path):
223 data = """
224entity test_entity is
225 generic (
226 buffer_segment_length_bytes : positive_vec_t(0 to 1));
227 port (
228 dummy_signal : out std_ulogic_vector(my_range_constant) := '0');end entity;
229"""
231 # entity->component, no ranges, and no default values.
232 expected = """\
233component test_entity is
234 generic (
235 buffer_segment_length_bytes : positive_vec_t
236 );
237 port (
238 dummy_signal : out std_ulogic_vector
239 );
240end component;"""
242 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
245def test_get_symbolator_component_last_port_parenthesis_on_same_line(tmp_path):
246 data = """
247entity test_entity is
248 generic (
249 buffer_segment_length_bytes : positive_vec_t(0 to 1) := (1, 2) )
250 ;
251 port (
252 dummy_signal : out std_ulogic_vector(my_range_constant) := '0' )
253 ;
254end entity;
255"""
257 # entity->component, no ranges, and no default values.
258 expected = """\
259component test_entity is
260 generic (
261 buffer_segment_length_bytes : positive_vec_t
262 );
263 port (
264 dummy_signal : out std_ulogic_vector
265 );
266end component;"""
268 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
271def test_get_symbolator_component_with_comments(tmp_path):
272 data = """
273entity test_entity is -- hello
274 generic ( -- test ); end entity; -- Comment --in a -- comment
275 apa : natural := 1-- ;
276-- hest : natural
277 );
278 port (
279 dummy : std_ulogic -- ); end entity;
280 -- := 0
281 );
282end entity;
283"""
285 expected = """\
286component test_entity is
287 generic (
288 apa : natural
289 );
290 port (
291 dummy : std_ulogic
292 );
293end component;"""
295 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
298def test_get_symbolator_component_with_separator_comments(tmp_path):
299 data = """
300entity test_entity is
301 port (
302 apa : out std_ulogic; -- trailing comment that shall be removed
303 --# {{}}
304 hest : out std_ulogic;
305-- Out of place comment that shall be removed
306-- foo : in std_ulogic;
307 --# {{test 123}}
308 zebra : out std_ulogic;
309 );
310end entity;
311"""
313 # entity->component, no ranges, and no default values.
314 expected = """\
315component test_entity is
316 port (
317 apa : out std_ulogic;
318 --# {{}}
319 hest : out std_ulogic;
320 --# {{test 123}}
321 zebra : out std_ulogic;
322 );
323end component;"""
325 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
328def test_get_symbolator_component_with_complex_array_width(tmp_path):
329 data = """
330entity test_entity is
331 port (
332 dummy : out std_ulogic_vector(
333 my_function(
334 value=>generic_value
335 ) - 1
336 downto 0
337 ) := (others => '0')
338 );
339end entity;
340"""
342 expected = """\
343component test_entity is
344 port (
345 dummy : out std_ulogic_vector
346 );
347end component;"""
349 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
352def run_get_symbolator_component_end_test(tmp_path, end_statement):
353 data = f"""
354entity test_entity is
355 port (
356 clk : in std_ulogic;
357 dummy_signal : out std_ulogic_vector(my_range_constant) := '0'
358 );
359{end_statement};
361architecture a of test_entity is
362begin
364end architecture;
365end;
366end a;
367"""
369 # entity->component, no ranges, and no default values.
370 expected = """\
371component test_entity is
372 port (
373 clk : in std_ulogic;
374 dummy_signal : out std_ulogic_vector
375 );
376end component;"""
378 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
381def run_get_symbolator_component_end_test_with_whitespace(tmp_path, end_statement):
382 # As above but with lots of whitespace around the keywords.
383 data = f"""
384entity
385 test_entity
386 is
388 port (
389 clk : in std_ulogic;
390 dummy_signal : out std_ulogic_vector(my_range_constant) := '0'
391 )
392 ;
395 {end_statement}
396 ;
398architecture a of test_entity is
399begin
401end architecture;
402end;
403end a;
404"""
406 # entity->component, no ranges, and no default values.
407 expected = """\
408component test_entity is
409 port (
410 clk : in std_ulogic;
411 dummy_signal : out std_ulogic_vector
412 );
413end component;"""
415 run_get_symbolator_component_test(tmp_path=tmp_path, vhdl_code=data, expected=expected)
418def test_get_symbolator_component_end_only_keyword(tmp_path):
419 end_statement = "end"
420 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement)
423def test_get_symbolator_component_no_end_entity_with_whitespace(tmp_path):
424 end_statement = "end \n"
425 run_get_symbolator_component_end_test_with_whitespace(
426 tmp_path=tmp_path, end_statement=end_statement
427 )
430def test_get_symbolator_component_end_name(tmp_path):
431 end_statement = "end test_entity"
432 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement)
435def test_get_symbolator_component_end_name_with_whitespace(tmp_path):
436 end_statement = "end \n test_entity \n"
437 run_get_symbolator_component_end_test_with_whitespace(
438 tmp_path=tmp_path, end_statement=end_statement
439 )
442def test_get_symbolator_component_end_entity_name(tmp_path):
443 end_statement = "end entity test_entity"
444 run_get_symbolator_component_end_test(tmp_path=tmp_path, end_statement=end_statement)
447def test_get_symbolator_component_end_entity_name_with_whitespace(tmp_path):
448 end_statement = "end \n entity \n test_entity \n"
449 run_get_symbolator_component_end_test_with_whitespace(
450 tmp_path=tmp_path, end_statement=end_statement
451 )