Coverage for tsfpga/vivado/test/test_build_result.py: 100%
24 statements
« prev ^ index » next coverage.py v7.6.9, created at 2024-12-07 20:51 +0000
« prev ^ index » next coverage.py v7.6.9, created at 2024-12-07 20:51 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9# First party libraries
10from tsfpga.vivado.build_result import BuildResult
13def test_size_summary():
14 build_result = BuildResult(name="apa")
16 build_result.synthesis_size = dict(LUT=3, FFs=4)
17 expected = """\
18Size of apa after synthesis:
19{
20 "LUT": 3,
21 "FFs": 4
22}"""
23 assert build_result.size_summary() == expected
25 build_result.implementation_size = dict(LUT=8, FFs=9)
26 expected = """\
27Size of apa after implementation:
28{
29 "LUT": 8,
30 "FFs": 9
31}"""
32 assert build_result.size_summary() == expected
35def test_report():
36 build_result = BuildResult(name="apa")
38 build_result.synthesis_size = dict(LUT=3, FFs=4)
39 expected = """\
40Size of apa after synthesis:
41{
42 "LUT": 3,
43 "FFs": 4
44}"""
45 assert build_result.report() == expected
47 # Add a logic level distribution report
48 build_result.logic_level_distribution = """\
49+-----------------+-------------+-----+----+---+----+
50| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
51+-----------------+-------------+-----+----+---+----+
52| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
53+-----------------+-------------+-----+----+---+----+\
54"""
55 expected = """\
56Size of apa after synthesis:
57{
58 "LUT": 3,
59 "FFs": 4
60}
61Logic level distribution:
62+-----------------+-------------+-----+----+---+----+
63| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
64+-----------------+-------------+-----+----+---+----+
65| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
66+-----------------+-------------+-----+----+---+----+\
67"""
68 assert build_result.report() == expected
69 assert build_result.maximum_logic_level == 3
72def test_maximum_logic_level_should_be_none_if_no_logic_level_distribution_is_set():
73 build_result = BuildResult(name="apa")
74 build_result.synthesis_size = dict(LUT=3, FFs=4)
76 # maximum_logic_level is calculated based on the logic_level_distribution, which is not set
77 # in this test case
78 assert build_result.logic_level_distribution is None
79 assert build_result.maximum_logic_level is None
80 assert "level" not in build_result.report()