Coverage for tsfpga/vivado/test/test_logic_level_distribution_parser.py: 100%
19 statements
« prev ^ index » next coverage.py v7.10.6, created at 2025-09-14 20:51 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9from tsfpga.vivado.logic_level_distribution_parser import LogicLevelDistributionParser
12def test_get_table():
13 report = """
151. Logic Level Distribution
16---------------------------
18+-----------------+-------------+-----+----+---+----+
19| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
20+-----------------+-------------+-----+----+---+----+
21| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
22+-----------------+-------------+-----+----+---+----+
23* Columns represent the logic levels per end point clock
24** Distribution is for top worst 1000 paths
25"""
26 expected = """\
27+-----------------+-------------+-----+----+---+----+
28| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
29+-----------------+-------------+-----+----+---+----+
30| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
31+-----------------+-------------+-----+----+---+----+\
32"""
33 assert LogicLevelDistributionParser.get_table(report) == expected
36def test_get_table_multiple():
37 report = """
391. Logic Level Distribution
40---------------------------
42+-----------------+-------------+-----+----+---+----+
43| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
44+-----------------+-------------+-----+----+---+----+
45| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
46| clk_fpga_1 | 3.000ns | 491 | 12 | 1 | 11 |
47+-----------------+-------------+-----+----+---+----+
48* Columns represent the logic levels per end point clock
49** Distribution is for top worst 1000 paths
50"""
51 expected = """\
52+-----------------+-------------+-----+----+---+----+
53| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
54+-----------------+-------------+-----+----+---+----+
55| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
56| clk_fpga_1 | 3.000ns | 491 | 12 | 1 | 11 |
57+-----------------+-------------+-----+----+---+----+\
58"""
59 assert LogicLevelDistributionParser.get_table(report) == expected
62def test_get_maximum_logic_level():
63 table = """\
64+-----------------+-------------+-----+----+---+----+
65| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
66+-----------------+-------------+-----+----+---+----+
67| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 1 |
68| clk_fpga_1 | 3.000ns | 491 | 12 | 1 | 11 |
69+-----------------+-------------+-----+----+---+----+\
70"""
71 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 3
73 table = """\
74+-----------------+-------------+-----+----+---+----+
75| End Point Clock | Requirement | 0 | 1 | 2 | 7 |
76+-----------------+-------------+-----+----+---+----+
77| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
78| clk_fpga_1 | 3.000ns | 491 | 12 | 1 | 1 |
79+-----------------+-------------+-----+----+---+----+\
80"""
81 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 7
83 table = """\
84+-----------------+-------------+-----+
85| End Point Clock | Requirement | 1 |
86+-----------------+-------------+-----+
87| clk_fpga_0 | 2.000ns | 491 |
88+-----------------+-------------+-----+
89"""
90 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 1
93def test_get_maximum_logic_level_no_paths():
94 table = """\
95+-----------------+-------------+
96| End Point Clock | Requirement |
97+-----------------+-------------+\
98"""
99 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 0