Coverage for tsfpga/vivado/test/test_logic_level_distribution_parser.py: 100%
15 statements
« prev ^ index » next coverage.py v7.6.7, created at 2024-11-20 20:51 +0000
1# --------------------------------------------------------------------------------------------------
2# Copyright (c) Lukas Vik. All rights reserved.
3#
4# This file is part of the tsfpga project, a project platform for modern FPGA development.
5# https://tsfpga.com
6# https://github.com/tsfpga/tsfpga
7# --------------------------------------------------------------------------------------------------
9# First party libraries
10from tsfpga.vivado.logic_level_distribution_parser import LogicLevelDistributionParser
13def test_get_table():
14 report = """
161. Logic Level Distribution
17---------------------------
19+-----------------+-------------+-----+----+---+----+
20| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
21+-----------------+-------------+-----+----+---+----+
22| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
23+-----------------+-------------+-----+----+---+----+
24* Columns represent the logic levels per end point clock
25** Distribution is for top worst 1000 paths
26"""
27 expected = """\
28+-----------------+-------------+-----+----+---+----+
29| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
30+-----------------+-------------+-----+----+---+----+
31| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
32+-----------------+-------------+-----+----+---+----+\
33"""
34 assert LogicLevelDistributionParser.get_table(report) == expected
37def test_get_maximum_logic_level():
38 table = """\
39+-----------------+-------------+-----+----+---+----+
40| End Point Clock | Requirement | 0 | 1 | 2 | 3 |
41+-----------------+-------------+-----+----+---+----+
42| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
43+-----------------+-------------+-----+----+---+----+\
44"""
45 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 3
47 table = """\
48+-----------------+-------------+-----+----+---+----+
49| End Point Clock | Requirement | 0 | 1 | 2 | 7 |
50+-----------------+-------------+-----+----+---+----+
51| clk_fpga_0 | 2.000ns | 491 | 12 | 1 | 11 |
52+-----------------+-------------+-----+----+---+----+\
53"""
54 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 7
56 table = """\
57+-----------------+-------------+-----+
58| End Point Clock | Requirement | 1 |
59+-----------------+-------------+-----+
60| clk_fpga_0 | 2.000ns | 491 |
61+-----------------+-------------+-----+
62"""
63 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 1
66def test_get_maximum_logic_level_no_paths():
67 table = """\
68+-----------------+-------------+
69| End Point Clock | Requirement |
70+-----------------+-------------+\
71"""
72 assert LogicLevelDistributionParser.get_maximum_logic_level(table) == 0