Coverage for tsfpga/yosys/test/test_utilization_parser.py: 100%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9from tsfpga.yosys.utilization_parser import ( 

10 YosysIntelUtilizationParser, 

11 YosysMicrochipUtilizationParser, 

12 YosysUtilizationParser, 

13 YosysXilinxUtilizationParser, 

14) 

15 

16# A cut-down version of a real report produced by the Yosys "stat" command. 

17REPORT = """ 

18=== smoke_top === 

19 

20 +----------Local Count, excluding submodules. 

21 | 

22 14 wires 

23 35 wire bits 

24 4 public wires 

25 25 public wire bits 

26 3 ports 

27 17 port bits 

28 26 cells 

29 1 BUFG 

30 8 FDRE 

31 9 IBUF 

32 8 OBUF 

33 

34End of script. Logfile hash: 304ba4a04e, time: 1.05s 

35""" 

36 

37 

38def test_get_size(): 

39 result = YosysUtilizationParser.get_size(report=REPORT) 

40 

41 assert result["BUFG"] == 1 

42 assert result["FDRE"] == 8 

43 assert result["IBUF"] == 9 

44 assert result["OBUF"] == 8 

45 

46 

47def test_get_size_does_not_aggregate_by_default(): 

48 report = """ 

49 10 cells 

50 3 LUT2 

51 2 LUT4 

52 1 LUT6 

53 4 FDRE 

54""" 

55 result = YosysUtilizationParser.get_size(report=report) 

56 

57 assert "Total LUTs" not in result 

58 assert "FFs" not in result 

59 assert result["LUT2"] == 3 

60 assert result["FDRE"] == 4 

61 

62 

63def test_get_size_aggregates_lut_count(): 

64 report = """ 

65 10 cells 

66 3 LUT2 

67 2 LUT4 

68 1 LUT6 

69 4 FDRE 

70""" 

71 result = YosysXilinxUtilizationParser.get_size(report=report) 

72 

73 assert result["Total LUTs"] == 6 

74 assert result["FFs"] == 4 

75 

76 

77def test_get_size_aggregates_ramb_and_dsp_counts(): 

78 report = """ 

79 4 cells 

80 1 RAMB18E2 

81 1 RAMB36E2 

82 2 DSP48E2 

83""" 

84 result = YosysXilinxUtilizationParser.get_size(report=report) 

85 

86 assert result["RAMB18"] == 1 

87 assert result["RAMB36"] == 1 

88 assert result["Block RAMs"] == 2 

89 assert result["DSP Blocks"] == 2 

90 assert result["RAMB18E2"] == 1 

91 assert result["RAMB36E2"] == 1 

92 assert result["DSP48E2"] == 2 

93 

94 

95def test_get_size_aggregates_intel_resource_counts(): 

96 report = """ 

97 19 cells 

98 1 $not 

99 8 dffeas 

100 10 fiftyfivenm_lcell_comb 

101 1 altsyncram 

102 1 fiftyfivenm_mac_mult 

103 1 fiftyfivenm_mac_out 

104""" 

105 result = YosysIntelUtilizationParser.get_size(report=report) 

106 

107 assert result["Total LUTs"] == 10 

108 assert result["FFs"] == 8 

109 assert result["Block RAMs"] == 1 

110 # One mapped multiplier yields both a "_mac_mult" and a "_mac_out" cell, but is one DSP. 

111 assert result["DSP Blocks"] == 1 

112 

113 

114def test_get_size_aggregates_microchip_resource_counts(): 

115 report = """ 

116 10 cells 

117 1 CFG1 

118 2 CFG2 

119 2 CFG4 

120 8 SLE 

121 1 RAM1K20 

122 1 MACC_PA 

123""" 

124 result = YosysMicrochipUtilizationParser.get_size(report=report) 

125 

126 assert result["Total LUTs"] == 5 

127 assert result["FFs"] == 8 

128 assert result["Block RAMs"] == 1 

129 assert result["DSP Blocks"] == 1 

130 

131 

132def test_get_size_ignores_scopeinfo_cells(): 

133 report = """ 

134 2 cells 

135 1 FDRE 

136 1 $scopeinfo 

137""" 

138 result = YosysUtilizationParser.get_size(report=report) 

139 

140 assert "$scopeinfo" not in result 

141 assert result["FDRE"] == 1 

142 

143 

144def test_get_size_with_no_cells_present(): 

145 report = """ 

146 0 cells 

147""" 

148 result = YosysXilinxUtilizationParser.get_size(report=report) 

149 

150 assert result["Total LUTs"] == 0 

151 assert result["FFs"] == 0 

152 assert result["RAMB36"] == 0 

153 assert result["RAMB18"] == 0 

154 assert result["Block RAMs"] == 0 

155 assert result["DSP Blocks"] == 0 

156 assert result["SRLs"] == 0 

157 

158 

159def test_get_size_with_duplicate_cell_names_are_summed(): 

160 report = """ 

161 2 cells 

162 1 FDRE 

163 1 FDRE 

164""" 

165 result = YosysUtilizationParser.get_size(report=report) 

166 

167 assert result["FDRE"] == 2