Coverage for tsfpga/examples/example_env.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9""" 

10Common functions and definitions in the example build environment. 

11""" 

12 

13# Standard libraries 

14from typing import TYPE_CHECKING, Optional 

15 

16if TYPE_CHECKING: 

17 from tsfpga.module_list import ModuleList 

18 

19# Import before others since it modifies PYTHONPATH. pylint: disable=unused-import 

20import tsfpga.examples.example_pythonpath # noqa: F401 

21 

22# Third party libraries 

23from hdl_registers.register import Register 

24from hdl_registers.register_modes import REGISTER_MODES 

25 

26# First party libraries 

27import tsfpga 

28from tsfpga.module import get_modules 

29 

30TSFPGA_EXAMPLES_TEMP_DIR = tsfpga.TSFPGA_GENERATED 

31 

32 

33def get_default_registers() -> list[Register]: 

34 """ 

35 Default registers for tsfpga examples. 

36 """ 

37 registers = [ 

38 Register("config", 0, REGISTER_MODES["r_w"], "Configuration register."), 

39 Register( 

40 "command", 

41 1, 

42 REGISTER_MODES["wpulse"], 

43 "When this register is written, all '1's in the written word will be asserted for one " 

44 "clock cycle in the FPGA logic.", 

45 ), 

46 Register("status", 2, REGISTER_MODES["r"], "Status register."), 

47 Register( 

48 "irq_status", 

49 3, 

50 REGISTER_MODES["r_wpulse"], 

51 "Reading a '1' in this register means the corresponding interrupt has triggered.\n" 

52 "Writing to this register will clear the interrupts where there is a '1' in the " 

53 "written word.", 

54 ), 

55 Register( 

56 "irq_mask", 

57 4, 

58 REGISTER_MODES["r_w"], 

59 "A '1' in this register means that the corresponding interrupt is enabled.", 

60 ), 

61 ] 

62 return registers 

63 

64 

65def get_tsfpga_example_modules( 

66 names_include: Optional[set[str]] = None, names_avoid: Optional[set[str]] = None 

67) -> "ModuleList": 

68 """ 

69 Wrapper of the regular :func:`.get_modules`. call with correct settings for tsfpga 

70 example modules. 

71 This will include the example tsfpga modules, but not the "real" modules. 

72 

73 Arguments will be passed on to :func:`.get_modules`. 

74 """ 

75 return get_modules( 

76 modules_folders=[tsfpga.TSFPGA_EXAMPLE_MODULES], 

77 names_include=names_include, 

78 names_avoid=names_avoid, 

79 library_name_has_lib_suffix=False, 

80 default_registers=get_default_registers(), 

81 ) 

82 

83 

84def get_hdl_modules( 

85 names_include: Optional[set[str]] = None, names_avoid: Optional[set[str]] = None 

86) -> "ModuleList": 

87 """ 

88 Wrapper of :func:`.get_modules` which returns the ``hdl-modules`` module objects 

89 (https://hdl-modules.com), if available. 

90 

91 If ``hdl-modules`` can not be found in the default repo checkout location, 

92 the function will assert False. 

93 

94 Arguments will be passed on to :func:`.get_modules`. 

95 

96 Return: 

97 :class:`.ModuleList`: The module objects. 

98 """ 

99 # Presumed location of the hdl-modules repo 

100 hdl_modules_repo_root = tsfpga.REPO_ROOT.parent.parent.resolve() / "hdl-modules" / "hdl-modules" 

101 if (hdl_modules_repo_root / "modules").exists(): 

102 return get_modules( 

103 modules_folders=[hdl_modules_repo_root / "modules"], 

104 names_include=names_include, 

105 names_avoid=names_avoid, 

106 library_name_has_lib_suffix=False, 

107 ) 

108 

109 raise FileNotFoundError( 

110 f"The hdl-modules modules could not be found. Searched in {hdl_modules_repo_root}" 

111 )