Coverage for tsfpga/examples/simulate.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# Standard libraries 

10import argparse 

11import sys 

12from pathlib import Path 

13from typing import TYPE_CHECKING, Any, Optional 

14 

15if TYPE_CHECKING: 

16 # First party libraries 

17 from tsfpga.module_list import ModuleList 

18 

19# Do PYTHONPATH insert() instead of append() to prefer any local repo checkout over any pip install 

20REPO_ROOT = Path(__file__).parent.parent.parent.resolve() 

21sys.path.insert(0, str(REPO_ROOT)) 

22 

23# Import before others since it modifies PYTHONPATH. pylint: disable=unused-import 

24import tsfpga.examples.example_pythonpath # noqa: F401 

25 

26# First party libraries 

27import tsfpga 

28import tsfpga.create_vhdl_ls_config 

29from tsfpga.create_ghdl_ls_config import create_ghdl_ls_configuration 

30from tsfpga.examples.example_env import ( 

31 TSFPGA_EXAMPLES_TEMP_DIR, 

32 get_hdl_modules, 

33 get_tsfpga_example_modules, 

34) 

35from tsfpga.examples.simulation_utils import ( 

36 SimulationProject, 

37 create_vhdl_ls_configuration, 

38 get_arguments_cli, 

39) 

40from tsfpga.git_simulation_subset import GitSimulationSubset 

41 

42 

43def main() -> None: 

44 """ 

45 Main function for the simulation flow. If you are setting up a new simulation environment 

46 you probably want to copy and modify this function. The other functions and classes 

47 should be reusable in most cases. 

48 """ 

49 cli = get_arguments_cli(default_output_path=TSFPGA_EXAMPLES_TEMP_DIR) 

50 args = cli.parse_args() 

51 

52 modules = get_tsfpga_example_modules() 

53 

54 # Avoid the module that depends on Xilinx unisim library 

55 module_names_avoid = set(["hard_fifo"]) if args.vivado_skip else None 

56 modules_no_sim = get_hdl_modules(names_avoid=module_names_avoid) 

57 

58 if args.vcs_minimal: 

59 if args.test_patterns != "*": 

60 sys.exit( 

61 "Can not specify a test pattern when using the --vcs-minimal flag." 

62 f" Got {args.test_patterns}", 

63 ) 

64 

65 test_filters = find_git_test_filters( 

66 args=args, 

67 repo_root=tsfpga.REPO_ROOT, 

68 modules=modules, 

69 modules_no_sim=modules_no_sim, 

70 reference_branch="origin/main", 

71 ) 

72 if not test_filters: 

73 print("Nothing to run. Appears to be no VHDL-related git diff.") 

74 return 

75 

76 # Override the test pattern argument to VUnit 

77 args.test_patterns = test_filters 

78 print(f"Running VUnit with test pattern {args.test_patterns}") 

79 

80 # Enable minimal compilation in VUnit 

81 args.minimal = True 

82 

83 simulation_project = SimulationProject(args=args) 

84 simulation_project.add_modules( 

85 args=args, 

86 modules=modules, 

87 modules_no_sim=modules_no_sim, 

88 include_verilog_files=False, 

89 include_systemverilog_files=False, 

90 ) 

91 simlib = simulation_project.add_vivado_simlib() 

92 ip_core_vivado_project_directory = simulation_project.add_vivado_ip_cores( 

93 modules=modules + modules_no_sim 

94 ) 

95 

96 create_vhdl_ls_configuration( 

97 output_path=tsfpga.REPO_ROOT, 

98 temp_files_path=TSFPGA_EXAMPLES_TEMP_DIR, 

99 modules=modules + modules_no_sim, 

100 ip_core_vivado_project_directory=ip_core_vivado_project_directory, 

101 ) 

102 

103 create_ghdl_ls_configuration( 

104 output_path=tsfpga.REPO_ROOT, 

105 modules=modules + modules_no_sim, 

106 vunit_proj=simulation_project.vunit_proj, 

107 simlib=simlib, 

108 ) 

109 

110 simulation_project.vunit_proj.main() 

111 

112 

113def find_git_test_filters( 

114 args: argparse.Namespace, 

115 repo_root: Path, 

116 modules: "ModuleList", 

117 modules_no_sim: Optional["ModuleList"] = None, 

118 reference_branch: str = "origin/master", 

119 **setup_vunit_kwargs: Any, 

120) -> list[str]: 

121 """ 

122 Construct a VUnit test filter that will run all test cases that are affected by git changes. 

123 The current git state is compared to a reference branch, and differences are derived. 

124 See :class:`.GitSimulationSubset` for details. 

125 

126 Arguments: 

127 args: Command line argument namespace. 

128 repo_root: Path to the repository root. Git commands will be run here. 

129 modules: Will be passed on to :meth:`.SimulationProject.add_modules`. 

130 modules_no_sim: Will be passed on to :meth:`.SimulationProject.add_modules`. 

131 reference_branch (str): The name of the reference branch that is used to collect a diff. 

132 setup_vunit_kwargs : Will be passed on to :meth:`.SimulationProject.add_modules`. 

133 

134 Return: 

135 A list of VUnit test case filters. 

136 """ 

137 # Set up a dummy VUnit project that will be used for dependency scanning. 

138 # Note that sources are added identical to the "real" project above. 

139 simulation_project = SimulationProject(args=args) 

140 simulation_project.add_modules( 

141 args=args, 

142 modules=modules, 

143 modules_no_sim=modules_no_sim, 

144 include_verilog_files=False, 

145 include_systemverilog_files=False, 

146 **setup_vunit_kwargs, 

147 ) 

148 

149 testbenches_to_run = GitSimulationSubset( 

150 repo_root=repo_root, 

151 reference_branch=reference_branch, 

152 vunit_proj=simulation_project.vunit_proj, 

153 ).find_subset() 

154 

155 test_filters = [] 

156 for testbench_file_name, library_name in testbenches_to_run: 

157 test_filters.append(f"{library_name}.{testbench_file_name}.*") 

158 

159 return test_filters 

160 

161 

162if __name__ == "__main__": 

163 main()