Coverage for tsfpga/examples/simulate.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9import sys 

10from pathlib import Path 

11 

12# Do PYTHONPATH insert() instead of append() to prefer any local repo checkout over any pip install. 

13REPO_ROOT = Path(__file__).parent.parent.parent.resolve() 

14sys.path.insert(0, str(REPO_ROOT)) 

15 

16# Import before others since it modifies PYTHONPATH. 

17import tsfpga.examples.example_pythonpath 

18 

19import tsfpga 

20import tsfpga.create_vhdl_ls_config 

21from tsfpga.create_ghdl_ls_config import create_ghdl_ls_configuration 

22from tsfpga.examples.example_env import ( 

23 TSFPGA_EXAMPLES_TEMP_DIR, 

24 get_hdl_modules, 

25 get_tsfpga_example_modules, 

26) 

27from tsfpga.examples.simulation_utils import ( 

28 NoVcsDiffTestsFound, 

29 SimulationProject, 

30 create_vhdl_ls_configuration, 

31 find_git_test_filter, 

32 get_arguments_cli, 

33) 

34 

35 

36def main() -> None: 

37 """ 

38 Main function for the simulation flow. If you are setting up a new simulation environment 

39 you probably want to copy and modify this function. The other functions and classes 

40 should be reusable in most cases. 

41 """ 

42 cli = get_arguments_cli(default_output_path=TSFPGA_EXAMPLES_TEMP_DIR) 

43 args = cli.parse_args() 

44 

45 modules = get_tsfpga_example_modules() 

46 modules_no_test = get_hdl_modules() 

47 

48 if args.vcs_minimal: 

49 try: 

50 args = find_git_test_filter( 

51 args=args, 

52 repo_root=tsfpga.REPO_ROOT, 

53 modules=modules, 

54 modules_no_test=modules_no_test, 

55 ) 

56 except NoVcsDiffTestsFound: 

57 print("Nothing to run. Appears to be no VHDL-related git diff.") 

58 return 

59 

60 simulation_project = SimulationProject(args=args) 

61 ip_core_vivado_project_directory = simulation_project.add_vivado_ip_cores( 

62 modules=modules + modules_no_test 

63 ) 

64 

65 # Generate before modules are added to VUnit project, to avoid duplicate files. 

66 create_vhdl_ls_configuration( 

67 output_path=tsfpga.REPO_ROOT, 

68 modules=modules + modules_no_test, 

69 vunit_proj=simulation_project.vunit_proj, 

70 ip_core_vivado_project_directory=ip_core_vivado_project_directory, 

71 ) 

72 

73 simulation_project.add_modules( 

74 args=args, 

75 modules=modules, 

76 modules_no_test=modules_no_test, 

77 include_verilog_files=False, 

78 include_systemverilog_files=False, 

79 ) 

80 

81 # Synopsys is needed by unisim MMCME2_ADV primitive. 

82 # Relaxed rules needed by unisim VITAL2000 package. 

83 # Do not use in any new code. 

84 simlib = simulation_project.add_vivado_simlib() 

85 simulation_project.vunit_proj.set_sim_option("ghdl.elab_flags", ["-fsynopsys", "-frelaxed"]) 

86 

87 create_ghdl_ls_configuration( 

88 output_path=tsfpga.REPO_ROOT, 

89 modules=modules + modules_no_test, 

90 vunit_proj=simulation_project.vunit_proj, 

91 simlib=simlib, 

92 ) 

93 

94 simulation_project.vunit_proj.main() 

95 

96 

97if __name__ == "__main__": 

98 main()