Coverage for tsfpga/examples/simulate.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9import sys 

10from pathlib import Path 

11 

12# Do PYTHONPATH insert() instead of append() to prefer any local repo checkout over any pip install. 

13REPO_ROOT = Path(__file__).parent.parent.parent.resolve() 

14sys.path.insert(0, str(REPO_ROOT)) 

15 

16# Import before others since it modifies PYTHONPATH. 

17import tsfpga.examples.example_pythonpath 

18 

19import tsfpga 

20from tsfpga.examples.example_env import ( 

21 TSFPGA_EXAMPLES_TEMP_DIR, 

22 get_hdl_modules, 

23 get_tsfpga_example_modules, 

24) 

25from tsfpga.examples.simulation_utils import ( 

26 SimulationProject, 

27 create_vhdl_ls_configuration, 

28 get_arguments_cli, 

29 set_git_test_pattern, 

30) 

31 

32 

33def main() -> None: 

34 """ 

35 Main function for the simulation flow. If you are setting up a new simulation environment 

36 you probably want to copy and modify this function. The other functions and classes 

37 should be reusable in most cases. 

38 """ 

39 cli = get_arguments_cli(default_output_path=TSFPGA_EXAMPLES_TEMP_DIR) 

40 args = cli.parse_args() 

41 

42 simulation_project = SimulationProject(args=args) 

43 

44 modules = get_tsfpga_example_modules() 

45 modules_no_test = get_hdl_modules() 

46 

47 if args.vcs_minimal and not set_git_test_pattern( 

48 args=args, 

49 repo_root=tsfpga.REPO_ROOT, 

50 vunit_proj=simulation_project.vunit_proj, 

51 modules=modules, 

52 ): 

53 # No git diff. Don't run anything. 

54 return 

55 

56 ip_core_vivado_project_directory = simulation_project.add_vivado_ip_cores( 

57 modules=modules + modules_no_test 

58 ) 

59 

60 # Generate before modules are added to VUnit project, to avoid duplicate files. 

61 create_vhdl_ls_configuration( 

62 output_path=tsfpga.REPO_ROOT, 

63 modules=modules + modules_no_test, 

64 vunit_proj=simulation_project.vunit_proj, 

65 ip_core_vivado_project_directory=ip_core_vivado_project_directory, 

66 ) 

67 

68 simulation_project.add_modules( 

69 modules=modules, 

70 modules_no_test=modules_no_test, 

71 include_verilog_files=False, 

72 include_systemverilog_files=False, 

73 ) 

74 

75 # Synopsys is needed by unisim MMCME2_ADV primitive. 

76 # Relaxed rules needed by unisim VITAL2000 package. 

77 # Do not use in any new code. 

78 simulation_project.add_vivado_simlib() 

79 simulation_project.vunit_proj.set_sim_option("ghdl.elab_flags", ["-fsynopsys", "-frelaxed"]) 

80 

81 simulation_project.vunit_proj.main() 

82 

83 

84if __name__ == "__main__": 

85 main()