Coverage for tsfpga/examples/simulate.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9import sys 

10from pathlib import Path 

11 

12# Do PYTHONPATH insert() instead of append() to prefer any local repo checkout over any pip install. 

13REPO_ROOT = Path(__file__).parent.parent.parent.resolve() 

14sys.path.insert(0, str(REPO_ROOT)) 

15 

16# Import before others since it modifies PYTHONPATH. 

17import tsfpga.examples.example_pythonpath 

18 

19import tsfpga 

20from tsfpga.create_ghdl_ls_config import create_ghdl_ls_configuration 

21from tsfpga.examples.example_env import ( 

22 TSFPGA_EXAMPLES_TEMP_DIR, 

23 get_hdl_modules, 

24 get_tsfpga_example_modules, 

25) 

26from tsfpga.examples.simulation_utils import ( 

27 NoVcsDiffTestsFound, 

28 SimulationProject, 

29 create_vhdl_ls_configuration, 

30 find_git_test_filter, 

31 get_arguments_cli, 

32) 

33 

34 

35def main() -> None: 

36 """ 

37 Main function for the simulation flow. If you are setting up a new simulation environment 

38 you probably want to copy and modify this function. The other functions and classes 

39 should be reusable in most cases. 

40 """ 

41 cli = get_arguments_cli(default_output_path=TSFPGA_EXAMPLES_TEMP_DIR) 

42 args = cli.parse_args() 

43 

44 modules = get_tsfpga_example_modules() 

45 modules_no_test = get_hdl_modules() 

46 

47 if args.vcs_minimal: 

48 try: 

49 args = find_git_test_filter( 

50 args=args, 

51 repo_root=tsfpga.REPO_ROOT, 

52 modules=modules, 

53 modules_no_test=modules_no_test, 

54 ) 

55 except NoVcsDiffTestsFound: 

56 print("Nothing to run. Appears to be no VHDL-related git diff.") 

57 return 

58 

59 simulation_project = SimulationProject(args=args) 

60 ip_core_vivado_project_directory = simulation_project.add_vivado_ip_cores( 

61 modules=modules + modules_no_test 

62 ) 

63 

64 # Generate before modules are added to VUnit project, to avoid duplicate files. 

65 create_vhdl_ls_configuration( 

66 output_path=tsfpga.REPO_ROOT, 

67 modules=modules + modules_no_test, 

68 vunit_proj=simulation_project.vunit_proj, 

69 ip_core_vivado_project_directory=ip_core_vivado_project_directory, 

70 ) 

71 

72 simulation_project.add_modules( 

73 args=args, 

74 modules=modules, 

75 modules_no_test=modules_no_test, 

76 include_verilog_files=False, 

77 include_systemverilog_files=False, 

78 ) 

79 

80 # Synopsys is needed by unisim MMCME2_ADV primitive. 

81 # Relaxed rules needed by unisim VITAL2000 package. 

82 # Do not use in any new code. 

83 simlib = simulation_project.add_vivado_simlib() 

84 simulation_project.vunit_proj.set_sim_option("ghdl.elab_flags", ["-fsynopsys", "-frelaxed"]) 

85 

86 create_ghdl_ls_configuration( 

87 output_path=tsfpga.REPO_ROOT, 

88 modules=modules + modules_no_test, 

89 vunit_proj=simulation_project.vunit_proj, 

90 simlib=simlib, 

91 ) 

92 

93 simulation_project.vunit_proj.main() 

94 

95 

96if __name__ == "__main__": 

97 main()