Coverage for tsfpga/examples/simulate.py: 0%

1# -------------------------------------------------------------------------------------------------- 

2# Copyright (c) Lukas Vik. All rights reserved. 

3# 

4# This file is part of the tsfpga project, a project platform for modern FPGA development. 

5# https://tsfpga.com 

6# https://github.com/tsfpga/tsfpga 

7# -------------------------------------------------------------------------------------------------- 

8 

9# Standard libraries 

10import sys 

11from pathlib import Path 

12 

13# Do PYTHONPATH insert() instead of append() to prefer any local repo checkout over any pip install. 

14REPO_ROOT = Path(__file__).parent.parent.parent.resolve() 

15sys.path.insert(0, str(REPO_ROOT)) 

16 

17# Import before others since it modifies PYTHONPATH. pylint: disable=unused-import 

18import tsfpga.examples.example_pythonpath # noqa: F401 

19 

20# First party libraries 

21import tsfpga 

22import tsfpga.create_vhdl_ls_config 

23from tsfpga.create_ghdl_ls_config import create_ghdl_ls_configuration 

24from tsfpga.examples.example_env import ( 

25 TSFPGA_EXAMPLES_TEMP_DIR, 

26 get_hdl_modules, 

27 get_tsfpga_example_modules, 

28) 

29from tsfpga.examples.simulation_utils import ( 

30 NoVcsDiffTestsFound, 

31 SimulationProject, 

32 create_vhdl_ls_configuration, 

33 find_git_test_filter, 

34 get_arguments_cli, 

35) 

36 

37 

38def main() -> None: 

39 """ 

40 Main function for the simulation flow. If you are setting up a new simulation environment 

41 you probably want to copy and modify this function. The other functions and classes 

42 should be reusable in most cases. 

43 """ 

44 cli = get_arguments_cli(default_output_path=TSFPGA_EXAMPLES_TEMP_DIR) 

45 args = cli.parse_args() 

46 

47 modules = get_tsfpga_example_modules() 

48 modules_no_test = get_hdl_modules() 

49 

50 if args.vcs_minimal: 

51 try: 

52 args = find_git_test_filter( 

53 args=args, 

54 repo_root=tsfpga.REPO_ROOT, 

55 modules=modules, 

56 modules_no_test=modules_no_test, 

57 ) 

58 except NoVcsDiffTestsFound: 

59 print("Nothing to run. Appears to be no VHDL-related git diff.") 

60 return 

61 

62 simulation_project = SimulationProject(args=args) 

63 ip_core_vivado_project_directory = simulation_project.add_vivado_ip_cores( 

64 modules=modules + modules_no_test 

65 ) 

66 

67 # Generate before modules are added to VUnit project, to avoid duplicate files. 

68 create_vhdl_ls_configuration( 

69 output_path=tsfpga.REPO_ROOT, 

70 modules=modules + modules_no_test, 

71 vunit_proj=simulation_project.vunit_proj, 

72 ip_core_vivado_project_directory=ip_core_vivado_project_directory, 

73 ) 

74 

75 simulation_project.add_modules( 

76 args=args, 

77 modules=modules, 

78 modules_no_test=modules_no_test, 

79 include_verilog_files=False, 

80 include_systemverilog_files=False, 

81 ) 

82 

83 # Synopsys is needed by unisim MMCME2_ADV primitive. 

84 # Relaxed rules needed by unisim VITAL2000 package. 

85 # Do not use in any new code. 

86 simlib = simulation_project.add_vivado_simlib() 

87 simulation_project.vunit_proj.set_sim_option("ghdl.elab_flags", ["-fsynopsys", "-frelaxed"]) 

88 

89 create_ghdl_ls_configuration( 

90 output_path=tsfpga.REPO_ROOT, 

91 modules=modules + modules_no_test, 

92 vunit_proj=simulation_project.vunit_proj, 

93 simlib=simlib, 

94 ) 

95 

96 simulation_project.vunit_proj.main() 

97 

98 

99if __name__ == "__main__": 

100 main()