tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
Date: 2021-07-26 04:08:16
Legend: low: >= 0% medium: >= 75.0% high: >= 90.0%
Exec Total Coverage
Lines: 4055 4512 89.9%
Branches: 14306 21609 66.2%

File Lines Branches
artyz7/artyz7_regs_pkg.vhd 100.0 100.0% 23 / 23 58.2% 57 / 98
artyz7/artyz7_top.vhd 100.0 100.0% 72 / 72 86.5% 378 / 437
artyz7/artyz7_top_pkg.vhd 100.0 100.0% 9 / 9 64.7% 11 / 17
artyz7/block_design_mock.vhd 100.0 100.0% 20 / 20 86.9% 206 / 237
artyz7/block_design_pkg.vhd 100.0 100.0% 1 / 1 50.0% 1 / 2
artyz7/block_design_wrapper.vhd 16.7 16.7% 11 / 66 36.9% 174 / 472
artyz7/tb_artyz7_top.vhd 100.0 100.0% 78 / 78 67.4% 244 / 362
artyz7/top_level_sim_pkg.vhd 100.0 100.0% 2 / 2 50.0% 4 / 8
axi/axi_address_fifo.vhd 100.0 100.0% 24 / 24 79.5% 70 / 88
axi/axi_b_fifo.vhd 100.0 100.0% 26 / 26 75.0% 63 / 84
axi/axi_lite_cdc.vhd 100.0 100.0% 31 / 31 70.0% 187 / 267
axi/axi_lite_mux.vhd 100.0 100.0% 89 / 89 68.7% 255 / 371
axi/axi_lite_pipeline.vhd 100.0 100.0% 31 / 31 74.1% 157 / 212
axi/axi_lite_pkg.vhd 100.0 100.0% 65 / 65 55.2% 112 / 203
axi/axi_lite_simple_read_crossbar.vhd 100.0 100.0% 26 / 26 80.4% 135 / 168
axi/axi_lite_simple_write_crossbar.vhd 100.0 100.0% 29 / 29 81.8% 180 / 220
axi/axi_lite_to_vec.vhd 100.0 100.0% 20 / 20 84.6% 204 / 241
axi/axi_pkg.vhd 0.0 0.0% 0 / 219 0.0% 0 / 613
axi/axi_r_fifo.vhd 100.0 100.0% 27 / 27 77.4% 82 / 106
axi/axi_read_cdc.vhd 100.0 100.0% 16 / 16 93.5% 86 / 92
axi/axi_read_throttle.vhd 100.0 100.0% 46 / 46 78.6% 173 / 220
axi/axi_simple_read_crossbar.vhd 100.0 100.0% 35 / 35 84.0% 147 / 175
axi/axi_simple_write_crossbar.vhd 100.0 100.0% 37 / 37 83.0% 195 / 235
axi/axi_stream_fifo.vhd 100.0 100.0% 21 / 21 71.9% 41 / 57
axi/axi_stream_pkg.vhd 0.0 0.0% 0 / 38 0.0% 0 / 117
axi/axi_to_axi_lite.vhd 100.0 100.0% 52 / 52 77.0% 244 / 317
axi/axi_to_axi_lite_vec.vhd 100.0 100.0% 19 / 19 92.1% 257 / 279
axi/axi_w_fifo.vhd 100.0 100.0% 24 / 24 73.9% 68 / 92
axi/axi_write_cdc.vhd 100.0 100.0% 17 / 17 94.7% 108 / 114
axi/axi_write_throttle.vhd 100.0 100.0% 47 / 47 80.1% 197 / 246
axi/tb_axi_cdc.vhd 100.0 100.0% 72 / 72 84.2% 390 / 463
axi/tb_axi_fifo.vhd 100.0 100.0% 59 / 59 80.5% 297 / 369
axi/tb_axi_lite_cdc.vhd 100.0 100.0% 47 / 47 70.3% 163 / 232
axi/tb_axi_lite_mux.vhd 100.0 100.0% 108 / 108 72.7% 431 / 593
axi/tb_axi_lite_pipeline.vhd 100.0 100.0% 43 / 43 70.5% 165 / 234
axi/tb_axi_lite_pkg.vhd 100.0 100.0% 33 / 33 60.4% 67 / 111
axi/tb_axi_pkg.vhd 100.0 100.0% 63 / 63 66.4% 93 / 140
axi/tb_axi_simple_crossbar.vhd 100.0 100.0% 82 / 82 81.8% 457 / 559
axi/tb_axi_stream_fifo.vhd 100.0 100.0% 38 / 38 56.7% 102 / 180
axi/tb_axi_stream_pkg.vhd 100.0 100.0% 23 / 23 57.3% 51 / 89
axi/tb_axi_to_axi_lite.vhd 100.0 100.0% 41 / 41 77.9% 247 / 317
axi/tb_axi_to_axi_lite_bus_error.vhd 100.0 100.0% 47 / 47 76.4% 256 / 335
axi/tb_axi_to_axi_lite_vec.vhd 100.0 100.0% 49 / 49 76.3% 254 / 333
bfm/axi_lite_master.vhd 0.0 0.0% 0 / 18 0.0% 0 / 211
bfm/axi_lite_read_slave.vhd 100.0 100.0% 19 / 19 66.4% 75 / 113
bfm/axi_lite_slave.vhd 100.0 100.0% 8 / 8 72.6% 61 / 84
bfm/axi_lite_write_slave.vhd 100.0 100.0% 22 / 22 67.0% 75 / 112
bfm/axi_master.vhd 100.0 100.0% 33 / 33 68.0% 187 / 275
bfm/axi_read_slave.vhd 0.0 0.0% 0 / 23 0.0% 0 / 166
bfm/axi_slave.vhd 100.0 100.0% 9 / 9 85.7% 102 / 119
bfm/axi_slave_pkg.vhd 0.0 0.0% 0 / 2 0.0% 0 / 102
bfm/axi_write_slave.vhd 0.0 0.0% 0 / 27 0.0% 0 / 168
bfm/bfm_pkg.vhd 35.3 35.3% 6 / 17 38.3% 59 / 154
common/addr_pkg.vhd 100.0 100.0% 16 / 16 63.0% 34 / 54
common/attribute_pkg.vhd 44.4 44.4% 4 / 9 30.0% 3 / 10
common/clock_counter.vhd 100.0 100.0% 18 / 18 75.0% 39 / 52
common/common_pkg.vhd 100.0 100.0% 3 / 3 50.0% 3 / 6
common/debounce.vhd 100.0 100.0% 13 / 13 63.9% 23 / 36
common/handshake_pipeline.vhd 100.0 100.0% 54 / 54 70.0% 147 / 210
common/handshake_splitter.vhd 100.0 100.0% 6 / 6 50.0% 5 / 10
common/periodic_pulser.vhd 100.0 100.0% 45 / 45 66.3% 61 / 92
common/tb_addr_pkg.vhd 100.0 100.0% 23 / 23 63.3% 76 / 120
common/tb_clock_counter.vhd 100.0 100.0% 25 / 25 62.0% 67 / 108
common/tb_debounce.vhd 100.0 100.0% 42 / 42 71.3% 134 / 188
common/tb_handshake_pipeline.vhd 100.0 100.0% 67 / 67 66.5% 187 / 281
common/tb_handshake_splitter.vhd 100.0 100.0% 68 / 68 63.8% 210 / 329
common/tb_periodic_pulser.vhd 100.0 100.0% 40 / 40 61.6% 93 / 151
common/tb_types_pkg.vhd 100.0 100.0% 71 / 71 50.0% 28 / 56
common/tb_width_conversion.vhd 96.3 96.3% 103 / 107 64.7% 278 / 430
common/types_pkg.vhd 87.2 87.2% 41 / 47 51.0% 74 / 145
common/width_conversion.vhd 100.0 100.0% 109 / 109 66.9% 249 / 372
ddr_buffer/ddr_buffer_regs_pkg.vhd 100.0 100.0% 21 / 21 60.3% 47 / 78
ddr_buffer/ddr_buffer_sim_pkg.vhd 100.0 100.0% 14 / 14 58.8% 90 / 153
ddr_buffer/ddr_buffer_top.vhd 100.0 100.0% 56 / 56 74.7% 219 / 293
ddr_buffer/example_reg_operations_pkg.vhd 100.0 100.0% 10 / 10 53.5% 68 / 127
ddr_buffer/tb_ddr_buffer.vhd 100.0 100.0% 46 / 46 73.6% 184 / 250
fifo/asynchronous_fifo.vhd 100.0 100.0% 65 / 65 71.9% 253 / 352
fifo/fifo.vhd 100.0 100.0% 53 / 53 70.9% 185 / 261
fifo/fifo_netlist_build_wrapper.vhd 0.0 0.0% 0 / 16 0.0% 0 / 38
fifo/fifo_wrapper.vhd 87.5 87.5% 28 / 32 44.7% 38 / 85
fifo/tb_asynchronous_fifo.vhd 100.0 100.0% 232 / 232 77.0% 743 / 965
fifo/tb_fifo.vhd 100.0 100.0% 192 / 192 75.0% 625 / 833
math/math_pkg.vhd 100.0 100.0% 49 / 49 52.6% 103 / 196
math/tb_math_pkg.vhd 100.0 100.0% 104 / 104 70.0% 298 / 426
math/tb_unsigned_divider.vhd 100.0 100.0% 39 / 39 64.4% 159 / 247
math/unsigned_divider.vhd 100.0 100.0% 34 / 34 62.4% 116 / 186
reg_file/axi_lite_reg_file.vhd 100.0 100.0% 64 / 64 71.5% 211 / 295
reg_file/axi_lite_reg_file_wrapper.vhd 0.0 0.0% 0 / 11 0.0% 0 / 90
reg_file/interrupt_register.vhd 100.0 100.0% 14 / 14 72.7% 8 / 11
reg_file/reg_file_pkg.vhd 100.0 100.0% 19 / 19 64.4% 58 / 90
reg_file/reg_operations_pkg.vhd 73.1 73.1% 49 / 67 55.4% 179 / 323
reg_file/tb_axi_lite_reg_file.vhd 100.0 100.0% 105 / 105 75.5% 426 / 564
reg_file/tb_interrupt_register.vhd 100.0 100.0% 53 / 53 73.0% 178 / 244
reg_file/tb_reg_file_pkg.vhd 100.0 100.0% 16 / 16 50.0% 29 / 58
reg_file/tb_reg_operations_pkg.vhd 100.0 100.0% 27 / 27 50.0% 29 / 58
resync/resync_counter.vhd 100.0 100.0% 14 / 14 75.9% 44 / 58
resync/resync_cycles.vhd 100.0 100.0% 24 / 24 77.0% 47 / 61
resync/resync_level.vhd 100.0 100.0% 13 / 13 72.5% 29 / 40
resync/resync_level_on_signal.vhd 100.0 100.0% 8 / 8 77.8% 14 / 18
resync/resync_pulse.vhd 100.0 100.0% 20 / 20 75.0% 15 / 20
resync/resync_slv_level.vhd 100.0 100.0% 5 / 5 71.4% 5 / 7
resync/resync_slv_level_coherent.vhd 100.0 100.0% 23 / 23 76.7% 46 / 60
resync/resync_slv_level_on_signal.vhd 100.0 100.0% 9 / 9 75.0% 6 / 8
resync/tb_resync_counter.vhd 100.0 100.0% 31 / 31 66.5% 113 / 170
resync/tb_resync_cycles.vhd 100.0 100.0% 51 / 51 68.6% 133 / 194
resync/tb_resync_pulse.vhd 100.0 100.0% 37 / 37 65.2% 92 / 141
resync/tb_resync_slv_level.vhd 100.0 100.0% 50 / 50 67.7% 130 / 192
resync/tb_resync_slv_level_on_signal.vhd 100.0 100.0% 32 / 32 67.7% 107 / 158