tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/artyz7_regs_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 23 23 100.0%
Branches: 57 98 58.2%

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138 -- This file is automatically generated by tsfpga.
2 -- Generated 2021-07-26 04:02 from file regs_artyz7.toml at commit 90600011cfdfc666.
3 -- Register hash e55b40b056f50e65c2b4fa285c7811cc53ddf423, generator version 1.0.5.
4
5 library ieee;
6 use ieee.std_logic_1164.all;
7 use ieee.numeric_std.all;
8
9 library reg_file;
10 use reg_file.reg_file_pkg.all;
11
12
13 package artyz7_regs_pkg is
14
15 12 constant artyz7_config : natural := 0;
16 12 constant artyz7_command : natural := 1;
17 12 constant artyz7_status : natural := 2;
18 12 constant artyz7_irq_status : natural := 3;
19 12 constant artyz7_irq_mask : natural := 4;
20 12 constant artyz7_plain_dummy_reg : natural := 5;
21 function artyz7_dummy_regs_array_dummy_reg(array_index : natural) return natural;
22 function artyz7_dummy_regs_second_array_dummy_reg(array_index : natural) return natural;
23 function artyz7_further_regs_dummy_reg(array_index : natural) return natural;
24
25 12 constant artyz7_dummy_regs_array_length : natural := 3;
26 12 constant artyz7_further_regs_array_length : natural := 1;
27
28 -- Declare register map constants here, but define them in body.
29 -- This is done so that functions have been elaborated when they are called.
30 subtype artyz7_reg_range is natural range 0 to 12;
31 constant artyz7_reg_map : reg_definition_vec_t(artyz7_reg_range);
32
33 subtype artyz7_regs_t is reg_vec_t(artyz7_reg_range);
34 constant artyz7_regs_init : artyz7_regs_t;
35
36 subtype artyz7_reg_was_accessed_t is std_logic_vector(artyz7_reg_range);
37
38 12 constant artyz7_plain_dummy_reg_plain_bit_a : natural := 0;
39 12 constant artyz7_plain_dummy_reg_plain_bit_b : natural := 1;
40 subtype artyz7_plain_dummy_reg_plain_bit_vector is natural range 5 downto 2;
41 12 constant artyz7_plain_dummy_reg_plain_bit_vector_width : positive := 4;
42
43 12 constant artyz7_dummy_regs_array_dummy_reg_array_bit_a : natural := 0;
44 12 constant artyz7_dummy_regs_array_dummy_reg_array_bit_b : natural := 1;
45 subtype artyz7_dummy_regs_array_dummy_reg_array_bit_vector is natural range 6 downto 2;
46 12 constant artyz7_dummy_regs_array_dummy_reg_array_bit_vector_width : positive := 5;
47
48 end package;
49
50 package body artyz7_regs_pkg is
51
52 function artyz7_dummy_regs_array_dummy_reg(array_index : natural) return natural is
53 begin
54
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54 assert array_index < artyz7_dummy_regs_array_length
55 report "Array index out of bounds: " & natural'image(array_index)
56 severity failure;
57
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54 return 6 + array_index * 2 + 0;
58 end function;
59
60 function artyz7_dummy_regs_second_array_dummy_reg(array_index : natural) return natural is
61 begin
62
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48 assert array_index < artyz7_dummy_regs_array_length
63 report "Array index out of bounds: " & natural'image(array_index)
64 severity failure;
65
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48 return 6 + array_index * 2 + 1;
66 end function;
67
68 function artyz7_further_regs_dummy_reg(array_index : natural) return natural is
69 begin
70
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12 assert array_index < artyz7_further_regs_array_length
71 report "Array index out of bounds: " & natural'image(array_index)
72 severity failure;
73
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24 return 12 + array_index * 1 + 0;
74 end function;
75
76
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168 constant artyz7_reg_map : reg_definition_vec_t(artyz7_reg_range) := (
77 0 => (idx => artyz7_config, reg_type => r_w),
78 1 => (idx => artyz7_command, reg_type => wpulse),
79 2 => (idx => artyz7_status, reg_type => r),
80 3 => (idx => artyz7_irq_status, reg_type => r_wpulse),
81 4 => (idx => artyz7_irq_mask, reg_type => r_w),
82 5 => (idx => artyz7_plain_dummy_reg, reg_type => r_w),
83 6 => (idx => artyz7_dummy_regs_array_dummy_reg(0), reg_type => r_w),
84 7 => (idx => artyz7_dummy_regs_second_array_dummy_reg(0), reg_type => r),
85 8 => (idx => artyz7_dummy_regs_array_dummy_reg(1), reg_type => r_w),
86 9 => (idx => artyz7_dummy_regs_second_array_dummy_reg(1), reg_type => r),
87 10 => (idx => artyz7_dummy_regs_array_dummy_reg(2), reg_type => r_w),
88 11 => (idx => artyz7_dummy_regs_second_array_dummy_reg(2), reg_type => r),
89 12 => (idx => artyz7_further_regs_dummy_reg(0), reg_type => r_w)
90 );
91
92
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168 constant artyz7_regs_init : artyz7_regs_t := (
93 0 => std_logic_vector(to_signed(0, 32)),
94 1 => std_logic_vector(to_signed(0, 32)),
95 2 => std_logic_vector(to_signed(0, 32)),
96 3 => std_logic_vector(to_signed(0, 32)),
97 4 => std_logic_vector(to_signed(0, 32)),
98 5 => std_logic_vector(to_signed(14, 32)),
99 6 => std_logic_vector(to_signed(49, 32)),
100 7 => std_logic_vector(to_signed(0, 32)),
101 8 => std_logic_vector(to_signed(49, 32)),
102 9 => std_logic_vector(to_signed(0, 32)),
103 10 => std_logic_vector(to_signed(49, 32)),
104 11 => std_logic_vector(to_signed(0, 32)),
105 12 => std_logic_vector(to_signed(0, 32))
106 );
107
108 end package body;
109