tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/artyz7_top.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library axi;
14 use axi.axi_pkg.all;
15 use axi.axi_lite_pkg.all;
16
17 library ddr_buffer;
18 library fifo;
19 library reg_file;
20 library resync;
21
22 use work.artyz7_top_pkg.all;
23 use work.artyz7_regs_pkg.all;
24
25
26
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6563 entity artyz7_top is
27 port (
28 clk_ext : in std_logic;
29
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3252 led : out std_logic_vector(0 to 3) := (others => '0');
30
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2394 dummy_output : out std_logic_vector(22 - 1 downto 0) := (others => '0')
31
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2202 );
32
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3432 end entity;
33 6642
34
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2532 architecture a of artyz7_top is
35 12
36
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78 signal clk_m_gp0 : std_logic := '0';
37
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11880 signal m_gp0_m2s : axi_m2s_t := axi_m2s_init;
38
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2748 signal m_gp0_s2m : axi_s2m_t := axi_s2m_init;
39 78
40 6 signal clk_s_hp0 : std_logic := '0';
41 2238 signal s_hp0_m2s : axi_m2s_t := axi_m2s_init;
42
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1170 signal s_hp0_s2m : axi_s2m_t := axi_s2m_init;
43
44
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12594 signal regs_m2s : axi_lite_m2s_vec_t(reg_slaves'range) := (others => axi_lite_m2s_init);
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9426 signal regs_s2m : axi_lite_s2m_vec_t(reg_slaves'range) := (others => axi_lite_s2m_init);
46
47
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498 begin
48 1074
49 ------------------------------------------------------------------------------
50 18 blink_0 : process
51
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186 variable count : unsigned(27 - 1 downto 0) := (others => '0');
52 begin
53 545 wait until rising_edge(clk_m_gp0);
54
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164 led(0) <= count(count'high);
55
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1334 count := count + 1;
56 end process;
57
58
59 ------------------------------------------------------------------------------
60 6 blink_1 : process
61
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198 variable count : unsigned(27 - 1 downto 0) := (others => '0');
62 begin
63
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1066 wait until rising_edge(clk_s_hp0);
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271 led(1) <= count(count'high);
65
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530 count := count + 1;
66 end process;
67 12
68 18
69 ------------------------------------------------------------------------------
70 12 regs_block : block
71 -- Set up some registers to be in same clock domain as AXI port,
72 12 -- and some to be in another clock domain.
73 60 constant clocks_are_the_same : boolean_vector(reg_slaves'range) :=
74
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204 (ddr_buffer_regs_idx => false, dummy_reg_slaves => true);
75 begin
76 12
77 ------------------------------------------------------------------------------
78
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6 axi_to_regs_inst : entity axi.axi_to_axi_lite_vec
79 generic map (
80
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12 axi_lite_slaves => reg_slaves,
81 clocks_are_the_same => clocks_are_the_same
82 12 )
83 port map (
84 clk_axi => clk_m_gp0,
85 axi_m2s => m_gp0_m2s,
86 12 axi_s2m => m_gp0_s2m,
87 --
88 clk_axi_lite_vec(ddr_buffer_regs_idx) => clk_s_hp0,
89 clk_axi_lite_vec(dummy_reg_slaves) => (dummy_reg_slaves => '0'),
90 axi_lite_m2s_vec => regs_m2s,
91 axi_lite_s2m_vec => regs_s2m
92 );
93
94
95 ------------------------------------------------------------------------------
96 register_maps : for slave in dummy_reg_slaves generate
97
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42 axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
98 generic map (
99 regs => artyz7_reg_map,
100 default_values => artyz7_regs_init
101 )
102 port map (
103 clk => clk_m_gp0,
104 --
105 axi_lite_m2s => regs_m2s(slave),
106 axi_lite_s2m => regs_s2m(slave)
107 );
108 end generate;
109 end block;
110
111
112 ------------------------------------------------------------------------------
113
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554 ddr_buffer_inst : entity ddr_buffer.ddr_buffer_top
114 port map (
115 clk => clk_s_hp0,
116 --
117 axi_read_m2s => s_hp0_m2s.read,
118 axi_read_s2m => s_hp0_s2m.read,
119 --
120 axi_write_m2s => s_hp0_m2s.write,
121 axi_write_s2m => s_hp0_s2m.write,
122 --
123 regs_m2s => regs_m2s(ddr_buffer_regs_idx),
124 regs_s2m => regs_s2m(ddr_buffer_regs_idx)
125 );
126
127
128 ------------------------------------------------------------------------------
129 block_design : block
130 6 signal pl_clk0, pl_clk1 : std_logic := '0';
131 begin
132
133
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1084 clk_m_gp0 <= pl_clk0;
134 clk_s_hp0 <= pl_clk1;
135
136 ------------------------------------------------------------------------------
137
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684 block_design_inst : entity work.block_design_wrapper
138 port map (
139 clk_m_gp0 => clk_m_gp0,
140 m_gp0_m2s => m_gp0_m2s,
141 m_gp0_s2m => m_gp0_s2m,
142 --
143 clk_s_hp0 => clk_s_hp0,
144 s_hp0_m2s => s_hp0_m2s,
145 s_hp0_s2m => s_hp0_s2m,
146 --
147 pl_clk0 => pl_clk0,
148 pl_clk1 => pl_clk1
149 );
150 end block;
151
152
153 ------------------------------------------------------------------------------
154 -- Build with an instance of each of the available resync block. To show that the constraints work
155 -- and the build passes timing.
156 resync_test_block : block
157
158 534 signal misc_dummy_input, dummy_output_m1 : std_logic_vector(dummy_output'range) :=
159 (others => '0');
160
161 -- Dummy signal in clk_ext domain
162 6 signal sample_value : std_logic := '0';
163 begin
164
165 -- Some dummy logic that instantiates a lot of the resync blocks.
166 -- All resync should be from internal clock to clk_ext.
167 138 assign_output : process
168 begin
169
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672 wait until rising_edge(clk_ext);
170
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4009 dummy_output <= dummy_output_m1;
171 end process;
172
173 -- Dummy bits for input.
174 -- Do not use more than the 32 bits that are actually assigned by the register bus.
175 -- Vivado will strip the logic since input will be '-'.
176
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1075 misc_dummy_input <= regs_m2s(ddr_buffer_regs_idx).write.w.data(misc_dummy_input'range);
177
178
179 ------------------------------------------------------------------------------
180
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30 resync_counter_inst : entity resync.resync_counter
181 generic map (
182 width => 4
183 )
184 port map (
185 clk_in => clk_s_hp0,
186 counter_in => unsigned(misc_dummy_input(3 downto 0)),
187 --
188 clk_out => clk_ext,
189 std_logic_vector(counter_out) => dummy_output_m1(3 downto 0)
190 );
191
192
193 ------------------------------------------------------------------------------
194 6 resync_cycles_inst : entity resync.resync_cycles
195 generic map (
196 counter_width => 8
197 )
198 port map (
199 clk_in => clk_s_hp0,
200 data_in => misc_dummy_input(4),
201 --
202 clk_out => clk_ext,
203 data_out => dummy_output_m1(4)
204 );
205
206
207 ------------------------------------------------------------------------------
208 6 resync_level_on_signal_inst : entity resync.resync_level_on_signal
209 port map (
210 data_in => misc_dummy_input(5),
211 --
212 clk_out => clk_ext,
213 sample_value => sample_value,
214 data_out => dummy_output_m1(5)
215 );
216
217
218 ------------------------------------------------------------------------------
219 6 resync_level_with_clk_in_inst : entity resync.resync_level
220 generic map (
221 enable_input_register => false
222 )
223 port map (
224 clk_in => clk_s_hp0,
225 data_in => misc_dummy_input(6),
226 --
227 clk_out => clk_ext,
228 data_out => dummy_output_m1(6)
229 );
230
231
232 ------------------------------------------------------------------------------
233 6 resync_level_with_clk_in_and_input_register_inst : entity resync.resync_level
234 generic map (
235 enable_input_register => true
236 )
237 port map (
238 clk_in => clk_s_hp0,
239 data_in => misc_dummy_input(7),
240 --
241 clk_out => clk_ext,
242 data_out => dummy_output_m1(7)
243 );
244
245
246 ------------------------------------------------------------------------------
247 38 resync_level_without_clk_in_inst : entity resync.resync_level
248 generic map (
249 enable_input_register => false
250 )
251 port map (
252 data_in => misc_dummy_input(8),
253 --
254 clk_out => clk_ext,
255 data_out => dummy_output_m1(8)
256 );
257
258
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32 sample_value <= dummy_output(8);
259
260
261 ------------------------------------------------------------------------------
262
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18 resync_slv_level_on_signal_inst : entity resync.resync_slv_level_on_signal
263 generic map (
264 width => 2
265 )
266 port map (
267 data_in => misc_dummy_input(10 downto 9),
268 --
269 clk_out => clk_ext,
270 sample_value => sample_value,
271 data_out => dummy_output_m1(10 downto 9)
272 );
273
274
275 ------------------------------------------------------------------------------
276
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18 resync_slv_level_without_clk_in_inst : entity resync.resync_slv_level
277 generic map (
278 width => 2,
279 enable_input_register => false
280 )
281 port map (
282 data_in => misc_dummy_input(12 downto 11),
283 --
284 clk_out => clk_ext,
285 data_out => dummy_output_m1(12 downto 11)
286 );
287
288
289 ------------------------------------------------------------------------------
290
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18 resync_slv_level_with_input_register_inst : entity resync.resync_slv_level
291 generic map (
292 width => 2,
293 enable_input_register => true
294 )
295 port map (
296 clk_in => clk_s_hp0,
297 data_in => misc_dummy_input(14 downto 13),
298 --
299 clk_out => clk_ext,
300 data_out => dummy_output_m1(14 downto 13)
301 );
302
303
304 ------------------------------------------------------------------------------
305
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62 resync_slv_level_coherent_inst : entity resync.resync_slv_level_coherent
306 generic map (
307 width => 2
308 )
309 port map (
310 clk_in => clk_s_hp0,
311 data_in => misc_dummy_input(16 downto 15),
312 --
313 clk_out => clk_ext,
314 data_out => dummy_output_m1(16 downto 15)
315 );
316
317
318 ------------------------------------------------------------------------------
319 asynchronous_fifo_block : block
320
321 -- We need to use a somewhat wide word in order to get Vivado to pack data in BRAM.
322 -- We do no want to use the same bits as some other resync, so for FIFO we use another
323 -- dummy input word.
324 6 alias fifo_dummy_input is regs_m2s(dummy_reg_slaves'low).write.w.data;
325 390 signal deep_read_data, shallow_read_data : std_logic_vector(16 - 1 downto 0) :=
326 (others => '0');
327 12 signal fifo_write_valid, fifo_read_ready : std_logic := '0';
328
329 begin
330
331
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45 fifo_write_valid <=
332 regs_s2m(dummy_reg_slaves'low).write.w.ready
333 and regs_m2s(dummy_reg_slaves'low).write.w.valid;
334
335
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115 dummy_output_m1(17) <= xor deep_read_data;
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115 dummy_output_m1(18) <= xor shallow_read_data;
337
338
339 ------------------------------------------------------------------------------
340
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6 deep_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
341 generic map (
342 width => deep_read_data'length,
343 -- Depth is selected to create a BRAM
344 depth => 1024
345 )
346 port map (
347 clk_read => clk_ext,
348 read_ready => fifo_read_ready,
349 read_valid => open,
350 read_data => deep_read_data,
351 --
352 clk_write => clk_m_gp0,
353 write_ready => open,
354 write_valid => fifo_write_valid,
355 write_data => fifo_dummy_input(31 downto 16)
356 );
357
358
359 ------------------------------------------------------------------------------
360
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6 shallow_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
361 generic map (
362 width => shallow_read_data'length,
363 -- Depth is selected to create a LUTRAM
364 depth => 16
365 )
366 port map (
367 clk_read => clk_ext,
368 read_ready => fifo_read_ready,
369 read_valid => open,
370 read_data => shallow_read_data,
371 --
372 clk_write => clk_m_gp0,
373 write_ready => open,
374 write_valid => fifo_write_valid,
375 write_data => fifo_dummy_input(15 downto 0)
376 );
377
378
379 ------------------------------------------------------------------------------
380 12 resync_pulse_inst : entity resync.resync_pulse
381 port map (
382 clk_in => clk_m_gp0,
383 pulse_in => fifo_write_valid,
384 --
385 clk_out => clk_ext,
386 pulse_out => fifo_read_ready
387 );
388
389 end block;
390
391 end block;
392
393 end architecture;
394