tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/artyz7_top_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 9 9 100.0%
Branches: 11 17 64.7%

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6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library common;
14 use common.addr_pkg.all;
15
16 library reg_file;
17 use reg_file.reg_file_pkg.all;
18
19
20 package artyz7_top_pkg is
21
22 ------------------------------------------------------------------------------
23 6 constant ddr_buffer_regs_idx : integer := 3;
24 subtype dummy_reg_slaves is integer range 0 to 2;
25
26 6 constant regs_addr_mask : addr_t := x"0000_f000";
27 6 constant ddr_buffer_regs_base_addr : addr_t := x"0000_3000";
28
29
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30 constant reg_slaves : addr_and_mask_vec_t(0 to 4 - 1) := (
30 0 => (addr => x"0000_0000", mask => regs_addr_mask),
31 1 => (addr => x"0000_1000", mask => regs_addr_mask),
32 2 => (addr => x"0000_2000", mask => regs_addr_mask),
33 ddr_buffer_regs_idx => (addr => ddr_buffer_regs_base_addr, mask => regs_addr_mask)
34 );
35
36
37 ------------------------------------------------------------------------------
38 6 constant m_gp0_data_width : integer := 32;
39 6 constant m_gp0_addr_width : integer := 32;
40
41 6 constant s_hp0_data_width : integer := 64;
42 6 constant s_hp0_addr_width : integer := 32;
43
44 end;
45