tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/common/attribute_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 866 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 package attribute_pkg is
10
11 -- Commonly used attributes. Descriptions from UG901 and UG912.
12
13 -- Prevent optimizations where signals are either optimized or absorbed into logic
14 -- blocks. Works in the same way as KEEP or KEEP_HIERARCHY attributes; However unlike
15 -- KEEP and KEEP_HIERARCHY, DONT_TOUCH is forward-annotated to place and route to
16 -- prevent logic optimization.
17 --
18 -- Use the DONT_TOUCH attribute in place of KEEP or KEEP_HIERARCHY.
19 --
20 -- Valid values: "true", "false"
21 attribute dont_touch : string;
22
23 -- Inform the tool that a register is capable of receiving asynchronous data in the D
24 -- input pin relative to the source clock, or that the register is a synchronizing
25 -- register within a synchronization chain.
26 --
27 -- Valid values: "true", "false"
28 attribute async_reg : string;
29
30 -- Instructs the Vivado synthesis tool on how to infer memory. Accepted values are:
31 -- * block: Instructs the tool to infer RAMB type components.
32 -- * distributed: Instructs the tool to infer the LUT RAMs.
33 -- * registers: Instructs the tool to infer registers instead of RAMs.
34 -- * ultra: Instructs the tool to use the UltraScale+TM URAM primitives.
35 attribute ram_style : string;
36 type ram_style_t is (
37 ram_style_block,
38 ram_style_distributed,
39 ram_style_registers,
40 ram_style_ultra,
41 ram_style_auto);
42 function to_attribute(ram_style_enum : ram_style_t) return string;
43
44 -- instructs the synthesis tool how to deal with synthesis arithmetic structures. By
45 -- default, unless there are timing concerns or threshold limits, synthesis attempts to
46 -- infer mults, mult-add, mult-sub, and mult-accumulate type structures into DSP blocks.
47 -- Adders, subtracters, and accumulators can go into these blocks also, but by default
48 -- are implemented with the logic instead of with DSP blocks.
49 --
50 -- Valid values: "yes", "no", "logic"
51 attribute use_dsp : string;
52
53 -- Indicates if a register should go into the I/O buffer. Place this attribute on the
54 -- register that you want in the I/O buffer.
55 --
56 -- Valid values: "true", "false"
57 attribute iob : string;
58
59 -- PULLUP applies a weak logic High on a tri-stateable output or bidirectional port to prevent it
60 -- from floating. The PULLUP property guarantees a logic High level to allow tri-stated nets to
61 -- avoid floating when not being driven.
62 --
63 -- Valid values: "true", "yes", "false", "no"
64 attribute pullup : string;
65
66 -- PULLDOWN applies a weak logic low level on a tri-stateable output or bidirectional port to
67 -- prevent it from floating. The PULLDOWN property guarantees a logic Low level to allow
68 -- tri-stated nets to avoid floating when not being driven.
69 --
70 -- Valid values: "true", "yes", "false", "no"
71 attribute pulldown : string;
72
73 end package;
74
75 package body attribute_pkg is
76
77 function to_attribute(ram_style_enum : ram_style_t) return string is
78 begin
79
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414 case ram_style_enum is
80 when ram_style_block =>
81 return "block";
82 when ram_style_distributed =>
83 return "distributed";
84 when ram_style_registers =>
85 return "registers";
86 when ram_style_ultra =>
87 return "ultra";
88 when ram_style_auto =>
89 414 return "auto";
90 when others =>
91 assert false severity failure;
92
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226 return "error";
93 end case;
94 end function;
95
96 end package body;
97