tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_address_fifo.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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Branches: 70 88 79.5%

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1 144 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- FIFO for AXI address channel (AR or AW). Can be used as clock crossing by setting
9 -- the "asynchronous" generic.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14
15 library common;
16 use common.attribute_pkg.all;
17
18 library fifo;
19
20 use work.axi_pkg.all;
21
22
23
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15894 entity axi_address_fifo is
24 generic (
25 id_width : natural;
26 addr_width : positive;
27 asynchronous : boolean;
28 depth : natural := 16;
29 ram_type : ram_style_t := ram_style_auto
30 );
31 port (
32 clk : in std_logic;
33 --
34 input_m2s : in axi_m2s_a_t;
35 input_s2m : out axi_s2m_a_t := axi_s2m_a_init;
36 20 --
37 output_m2s : out axi_m2s_a_t := axi_m2s_a_init;
38 20 output_s2m : in axi_s2m_a_t;
39 20 -- Only need to assign the clock if generic asynchronous is "True"
40 clk_input : in std_logic := '0'
41 20 );
42 20 end entity;
43 2732
44 68 architecture a of axi_address_fifo is
45
46 begin
47 20
48 passthrough_or_fifo : if depth = 0 generate
49 613468 output_m2s <= input_m2s;
50
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45644 input_s2m <= output_s2m;
51 20
52 20 else generate
53 924
54 40 constant ar_width : integer := axi_m2s_a_sz(id_width, addr_width);
55
56 20 signal read_valid : std_logic := '0';
57
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1872 signal read_data, write_data : std_logic_vector(ar_width - 1 downto 0);
58
59 20 begin
60
61 ------------------------------------------------------------------------------
62 5888 assign : process(all)
63 begin
64
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3236106 write_data <= to_slv(input_m2s, id_width, addr_width);
65
66
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7144692 output_m2s <= to_axi_m2s_a(read_data, id_width, addr_width);
67
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70046 output_m2s.valid <= read_valid;
68 end process;
69
70
71 ------------------------------------------------------------------------------
72
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44 fifo_wrapper_inst : entity fifo.fifo_wrapper
73 generic map (
74 use_asynchronous_fifo => asynchronous,
75 width => ar_width,
76 depth => depth,
77 ram_type => ram_type
78 )
79 port map(
80 clk => clk,
81 clk_read => clk,
82 clk_write => clk_input,
83 --
84 read_ready => output_s2m.ready,
85 read_valid => read_valid,
86 read_data => read_data,
87 --
88 write_ready => input_s2m.ready,
89 write_valid => input_m2s.valid,
90 write_data => write_data
91 );
92
93 end generate;
94
95 end architecture;
96