tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_b_fifo.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 26 26 100.0%
Branches: 63 84 75.0%

Line Branch Exec Source
1 72 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- FIFO for AXI write response channel (B). Can be used as clock crossing by setting
9 -- the "asynchronous" generic.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14
15 library fifo;
16
17 library common;
18 use common.attribute_pkg.all;
19
20 use work.axi_pkg.all;
21
22
23
9/10
✗ Branch 0 not taken.
✓ Branch 1 taken 12 times.
✓ Branch 3 taken 288 times.
✓ Branch 4 taken 24 times.
✓ Branch 6 taken 24 times.
✓ Branch 7 taken 24 times.
✓ Branch 11 taken 288 times.
✓ Branch 12 taken 12 times.
✓ Branch 14 taken 24 times.
✓ Branch 15 taken 12 times.
3346 entity axi_b_fifo is
24 generic (
25 id_width : natural;
26 asynchronous : boolean;
27 depth : natural := 16;
28 ram_type : ram_style_t := ram_style_auto
29 );
30 port (
31 clk : in std_logic;
32 --
33 input_m2s : in axi_m2s_b_t;
34 input_s2m : out axi_s2m_b_t := axi_s2m_b_init;
35 --
36 10 output_m2s : out axi_m2s_b_t := axi_m2s_b_init;
37 output_s2m : in axi_s2m_b_t;
38 10 -- Only need to assign the clock if generic asynchronous is "True"
39 10 clk_input : in std_logic := '0'
40 );
41 10 end entity;
42 10
43
8/10
✗ Branch 0 not taken.
✓ Branch 1 taken 10 times.
✓ Branch 6 taken 70 times.
✓ Branch 7 taken 10 times.
✗ Branch 8 not taken.
✓ Branch 9 taken 10 times.
✓ Branch 11 taken 70 times.
✓ Branch 12 taken 10 times.
✓ Branch 13 taken 70 times.
✓ Branch 14 taken 10 times.
244 architecture a of axi_b_fifo is
44 10
45 begin
46
47
1/2
✗ Branch 0 not taken.
✓ Branch 1 taken 10 times.
10 passthrough_or_fifo : if depth = 0 generate
48 4022 output_m2s <= input_m2s;
49
13/16
✗ Branch 3 not taken.
✓ Branch 4 taken 2006 times.
✓ Branch 5 taken 2000 times.
✓ Branch 6 taken 6 times.
✓ Branch 8 taken 48144 times.
✓ Branch 9 taken 2006 times.
✗ Branch 10 not taken.
✓ Branch 11 taken 48144 times.
✓ Branch 12 taken 20 times.
✓ Branch 13 taken 48124 times.
✓ Branch 15 taken 4012 times.
✓ Branch 16 taken 2006 times.
✗ Branch 17 not taken.
✓ Branch 18 taken 4012 times.
✓ Branch 19 taken 8 times.
✓ Branch 20 taken 4004 times.
54278 input_s2m <= output_s2m;
50
51 10 else generate
52 10
53
4/6
✗ Branch 0 not taken.
✓ Branch 1 taken 10 times.
✗ Branch 5 not taken.
✓ Branch 6 taken 10 times.
✓ Branch 8 taken 70 times.
✓ Branch 9 taken 10 times.
90 constant b_width : integer := axi_s2m_b_sz(id_width);
54 10
55 150 signal write_data, read_data : std_logic_vector(b_width - 1 downto 0);
56 22 signal read_valid : std_logic := '0';
57 10
58 begin
59 10
60 ------------------------------------------------------------------------------
61 670 assign : process(all)
62 10 begin
63
13/16
✗ Branch 1 not taken.
✓ Branch 2 taken 20044 times.
✓ Branch 3 taken 5000 times.
✓ Branch 4 taken 15044 times.
✓ Branch 6 taken 481056 times.
✓ Branch 7 taken 20044 times.
✗ Branch 8 not taken.
✓ Branch 9 taken 481056 times.
✓ Branch 10 taken 80 times.
✓ Branch 11 taken 480976 times.
✓ Branch 13 taken 40088 times.
✓ Branch 14 taken 20044 times.
✗ Branch 15 not taken.
✓ Branch 16 taken 40088 times.
✓ Branch 17 taken 32 times.
✓ Branch 18 taken 40056 times.
541188 input_s2m <= to_axi_s2m_b(read_data, id_width);
64
3/4
✗ Branch 0 not taken.
✓ Branch 1 taken 20044 times.
✓ Branch 2 taken 10000 times.
✓ Branch 3 taken 10044 times.
20044 input_s2m.valid <= read_valid;
65
66
7/10
✓ Branch 2 taken 20044 times.
✗ Branch 3 not taken.
✗ Branch 4 not taken.
✓ Branch 5 taken 20044 times.
✓ Branch 8 taken 140308 times.
✓ Branch 9 taken 20044 times.
✗ Branch 10 not taken.
✓ Branch 11 taken 140308 times.
✓ Branch 12 taken 194 times.
✓ Branch 13 taken 140114 times.
160352 write_data <= to_slv(output_s2m, id_width);
67 end process;
68
69
70 ------------------------------------------------------------------------------
71
5/10
✗ Branch 3 not taken.
✓ Branch 4 taken 10 times.
✗ Branch 6 not taken.
✓ Branch 7 taken 10 times.
✗ Branch 8 not taken.
✓ Branch 9 taken 10 times.
✗ Branch 11 not taken.
✓ Branch 12 taken 10 times.
✗ Branch 13 not taken.
✓ Branch 14 taken 10 times.
22 fifo_wrapper_inst : entity fifo.fifo_wrapper
72 generic map (
73 use_asynchronous_fifo => asynchronous,
74 width => b_width,
75 depth => depth,
76 ram_type => ram_type
77 )
78 port map(
79 clk => clk,
80 clk_read => clk_input,
81 clk_write => clk,
82 --
83 read_ready => input_m2s.ready,
84 read_valid => read_valid,
85 read_data => read_data,
86 --
87 write_ready => output_m2s.ready,
88 write_valid => output_s2m.valid,
89 write_data => write_data
90 );
91
92 end generate;
93
94 end architecture;
95