tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_lite_cdc.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 102 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Clock crossing of an AXI-Lite bus
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library common;
16 use common.attribute_pkg.all;
17
18 library fifo;
19
20 use work.axi_lite_pkg.all;
21 use work.axi_pkg.all;
22
23
24
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30811 entity axi_lite_cdc is
25 generic (
26 data_width : positive;
27 addr_width : positive;
28 fifo_depth : positive := 16;
29 ram_type : ram_style_t := ram_style_auto
30 );
31 port (
32 clk_master : in std_logic;
33 master_m2s : in axi_lite_m2s_t;
34 master_s2m : out axi_lite_s2m_t := axi_lite_s2m_init;
35 --
36 clk_slave : in std_logic;
37 slave_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
38 slave_s2m : in axi_lite_s2m_t
39 );
40 end entity;
41
42 architecture a of axi_lite_cdc is
43
44 85 begin
45 85
46 ------------------------------------------------------------------------------
47 85 aw_block : block
48
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6078 signal read_data, write_data : std_logic_vector(addr_width - 1 downto 0);
49 begin
50 85
51 316928 slave_m2s.write.aw.addr(read_data'range) <= unsigned(read_data);
52
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159517 write_data <= std_logic_vector(master_m2s.write.aw.addr(write_data'range));
53
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24948 aw_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
55 generic map (
56 width => axi_lite_m2s_a_sz(addr_width),
57 depth => fifo_depth,
58 ram_type => ram_type
59 )
60 port map(
61
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85 clk_read => clk_slave,
62 read_ready => slave_s2m.write.aw.ready,
63 read_valid => slave_m2s.write.aw.valid,
64 read_data => read_data,
65 --
66 clk_write => clk_master,
67 85 write_ready => master_s2m.write.aw.ready,
68 write_valid => master_m2s.write.aw.valid,
69 write_data => write_data
70 85 );
71 end block;
72
73
74
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1885 ------------------------------------------------------------------------------
75 w_block : block
76 102 constant w_width : integer := axi_lite_m2s_w_sz(data_width);
77 1241 signal write_data, read_data : std_logic_vector(w_width - 1 downto 0);
78 begin
79
80
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1621212 slave_m2s.write.w.data <= to_axi_lite_m2s_w(read_data, data_width).data;
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112878 slave_m2s.write.w.strb <= to_axi_lite_m2s_w(read_data, data_width).strb;
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693727 write_data <= to_slv(master_m2s.write.w, data_width);
83
84
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17 w_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
85 generic map (
86 85 width => w_width,
87 depth => fifo_depth,
88 ram_type => ram_type
89 )
90 port map(
91 clk_read => clk_slave,
92 read_ready => slave_s2m.write.w.ready,
93 read_valid => slave_m2s.write.w.valid,
94 read_data => read_data,
95 --
96 clk_write => clk_master,
97 write_ready => master_s2m.write.w.ready,
98 write_valid => master_m2s.write.w.valid,
99 write_data => write_data
100 );
101 end block;
102
103
104 ------------------------------------------------------------------------------
105
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25084 b_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
106 generic map (
107 width => axi_lite_s2m_b_sz,
108 depth => fifo_depth,
109 ram_type => ram_type
110 )
111 port map(
112 clk_read => clk_master,
113 read_ready => master_m2s.write.b.ready,
114 read_valid => master_s2m.write.b.valid,
115 read_data => master_s2m.write.b.resp,
116 --
117 clk_write => clk_slave,
118 write_ready => slave_m2s.write.b.ready,
119 write_valid => slave_s2m.write.b.valid,
120 write_data => slave_s2m.write.b.resp
121 );
122
123
124 ------------------------------------------------------------------------------
125 ar_block : block
126 593 signal read_data, write_data : std_logic_vector(addr_width - 1 downto 0);
127 begin
128
129
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629400 slave_m2s.read.ar.addr(read_data'range) <= unsigned(read_data);
130 write_data <= std_logic_vector(master_m2s.read.ar.addr(write_data'range));
131
132
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25096 ar_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
133 generic map (
134 width => axi_lite_m2s_a_sz(addr_width),
135 depth => fifo_depth,
136 ram_type => ram_type
137 )
138 port map(
139 clk_read => clk_slave,
140 read_ready => slave_s2m.read.ar.ready,
141 read_valid => slave_m2s.read.ar.valid,
142 read_data => read_data,
143 --
144 clk_write => clk_master,
145 write_ready => master_s2m.read.ar.ready,
146 write_valid => master_m2s.read.ar.valid,
147 write_data => write_data
148 );
149 end block;
150
151
152 ------------------------------------------------------------------------------
153 r_block : block
154 17 constant r_width : integer := axi_lite_s2m_r_sz(data_width);
155 1190 signal read_data, write_data : std_logic_vector(r_width - 1 downto 0);
156 begin
157
158
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1643244 master_s2m.read.r.data <= to_axi_lite_s2m_r(read_data, data_width).data;
159
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38222 master_s2m.read.r.resp <= to_axi_lite_s2m_r(read_data, data_width).resp;
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440372 write_data <= to_slv(slave_s2m.read.r, data_width);
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34 r_asynchronous_fifo_inst : entity fifo.asynchronous_fifo
163 generic map (
164 width => r_width,
165 depth => fifo_depth,
166 ram_type => ram_type
167 )
168 port map(
169 clk_read => clk_master,
170 read_ready => master_m2s.read.r.ready,
171 read_valid => master_s2m.read.r.valid,
172 read_data => read_data,
173 --
174 clk_write => clk_slave,
175 write_ready => slave_m2s.read.r.ready,
176 write_valid => slave_s2m.read.r.valid,
177 write_data => write_data
178 );
179 end block;
180
181 end architecture;
182