tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_lite_master.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 0 18 0.0%
Branches: 0 211 0.0%

Line Branch Exec Source
1 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library math;
14 use math.math_pkg.all;
15
16 library axi;
17 use axi.axi_lite_pkg.all;
18
19 library vunit_lib;
20 context vunit_lib.vunit_context;
21 context vunit_lib.vc_context;
22
23
24 entity axi_lite_master is
25 generic (
26 bus_handle : bus_master_t
27 );
28 port (
29 clk : in std_logic;
30
31 axi_lite_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
32 axi_lite_s2m : in axi_lite_s2m_t := axi_lite_s2m_init
33 );
34 end entity;
35
36 architecture a of axi_lite_master is
37
38 signal rdata, wdata : std_logic_vector(data_length(bus_handle) - 1 downto 0);
39 signal wstrb : std_logic_vector(byte_enable_length(bus_handle) - 1 downto 0);
40
41 signal araddr, awaddr : std_logic_vector(address_length(bus_handle) - 1 downto 0);
42
43 begin
44
45 ------------------------------------------------------------------------------
46 axi_lite_m2s.read.ar.addr(araddr'range) <= unsigned(araddr);
47 rdata <= axi_lite_s2m.read.r.data(rdata'range);
48
49 axi_lite_m2s.write.aw.addr(awaddr'range) <= unsigned(awaddr);
50 axi_lite_m2s.write.w.data(wdata'range) <= wdata;
51 axi_lite_m2s.write.w.strb(wstrb'range) <= wstrb;
52
53
54 ------------------------------------------------------------------------------
55 axi_lite_master_inst : entity vunit_lib.axi_lite_master
56 generic map (
57 bus_handle => bus_handle
58 )
59 port map (
60 aclk => clk,
61
62 arready => axi_lite_s2m.read.ar.ready,
63 arvalid => axi_lite_m2s.read.ar.valid,
64 araddr => araddr,
65
66 rready => axi_lite_m2s.read.r.ready,
67 rvalid => axi_lite_s2m.read.r.valid,
68 rdata => rdata,
69 rresp => axi_lite_s2m.read.r.resp,
70
71 awready => axi_lite_s2m.write.aw.ready,
72 awvalid => axi_lite_m2s.write.aw.valid,
73 awaddr => awaddr,
74
75 wready => axi_lite_s2m.write.w.ready,
76 wvalid => axi_lite_m2s.write.w.valid,
77 wdata => wdata,
78 wstrb => wstrb,
79
80 bready => axi_lite_m2s.write.b.ready,
81 bvalid => axi_lite_s2m.write.b.valid,
82 bresp => axi_lite_s2m.write.b.resp
83 );
84
85 end architecture;
86