tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_lite_pipeline.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Pipelining of an AXI-Lite bus. Full throughput and improved timing characteristics are achieved
9 -- through the use of skid buffers. However to generics to handshake_pipeline can be modified to
10 -- get a simpler handshake_pipeline implementation that results in lower resource utilizatoin.
11 -- -------------------------------------------------------------------------------------------------
12
13 library ieee;
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
16
17 library common;
18
19 use work.axi_lite_pkg.all;
20 use work.axi_pkg.all;
21
22
23
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4248 entity axi_lite_pipeline is
24 generic (
25 data_width : positive;
26 addr_width : positive;
27 -- Settings to the handshake_pipeline blocks. These default settings (the same as
28 -- handshake_pipeline's defaults) give full throughput and the lowest logic depth.
29 10 -- They can be changed from default in order to decrease logic utilization.
30 full_throughput : boolean := true;
31 10 allow_poor_input_ready_timing : boolean := false
32 10 );
33 10 port (
34
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232 clk : in std_logic;
35 --
36 10 master_m2s : in axi_lite_m2s_t;
37 10 master_s2m : out axi_lite_s2m_t := axi_lite_s2m_init;
38 10 --
39
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676 slave_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
40 slave_s2m : in axi_lite_s2m_t
41 );
42 end entity;
43
44 architecture a of axi_lite_pipeline is
45
46 begin
47
48 ------------------------------------------------------------------------------
49 aw_block : block
50 80 signal output_data, input_data : std_logic_vector(addr_width - 1 downto 0);
51 begin
52
53 54008 slave_m2s.write.aw.addr(output_data'range) <= unsigned(output_data);
54
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51920 input_data <= std_logic_vector(master_m2s.write.aw.addr(input_data'range));
55
56 4128 aw_handshake_pipeline_inst : entity common.handshake_pipeline
57 generic map (
58 data_width => axi_lite_m2s_a_sz(addr_width),
59 full_throughput => full_throughput,
60 allow_poor_input_ready_timing => allow_poor_input_ready_timing
61 )
62 port map(
63 clk => clk,
64 --
65 input_ready => master_s2m.write.aw.ready,
66 input_valid => master_m2s.write.aw.valid,
67 input_data => input_data,
68 --
69 output_ready => slave_s2m.write.aw.ready,
70 output_valid => slave_m2s.write.aw.valid,
71 output_data => output_data
72 );
73 end block;
74
75
76 ------------------------------------------------------------------------------
77 w_block : block
78 2 constant w_width : integer := axi_lite_m2s_w_sz(data_width);
79 146 signal master_m2s_w, slave_m2s_w : std_logic_vector(w_width - 1 downto 0);
80 begin
81
82
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270324 slave_m2s.write.w.data <= to_axi_lite_m2s_w(slave_m2s_w, data_width).data;
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18648 slave_m2s.write.w.strb <= to_axi_lite_m2s_w(slave_m2s_w, data_width).strb;
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231283 master_m2s_w <= to_slv(master_m2s.write.w, data_width);
85
86 2 handshake_pipeline_inst : entity common.handshake_pipeline
87 generic map (
88 data_width => w_width,
89 full_throughput => full_throughput,
90 allow_poor_input_ready_timing => allow_poor_input_ready_timing
91 )
92 port map(
93 clk => clk,
94 --
95 input_ready => master_s2m.write.w.ready,
96 input_valid => master_m2s.write.w.valid,
97 input_data => master_m2s_w,
98 --
99 output_ready => slave_s2m.write.w.ready,
100 output_valid => slave_m2s.write.w.valid,
101 output_data => slave_m2s_w
102 );
103 end block;
104
105
106 ------------------------------------------------------------------------------
107
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4244 b_handshake_pipeline_inst : entity common.handshake_pipeline
108 generic map (
109 data_width => axi_lite_s2m_b_sz,
110 full_throughput => full_throughput,
111 allow_poor_input_ready_timing => allow_poor_input_ready_timing
112 )
113 port map(
114 clk => clk,
115 --
116 input_ready => slave_m2s.write.b.ready,
117 input_valid => slave_s2m.write.b.valid,
118 input_data => slave_s2m.write.b.resp,
119 --
120 output_ready => master_m2s.write.b.ready,
121 output_valid => master_s2m.write.b.valid,
122 output_data => master_s2m.write.b.resp
123 );
124
125
126 ------------------------------------------------------------------------------
127 ar_block : block
128 80 signal output_data, input_data : std_logic_vector(addr_width - 1 downto 0);
129 begin
130
131
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106904 slave_m2s.read.ar.addr(output_data'range) <= unsigned(output_data);
132 input_data <= std_logic_vector(master_m2s.read.ar.addr(input_data'range));
133
134 4128 ar_handshake_pipeline_inst : entity common.handshake_pipeline
135 generic map (
136 data_width => axi_lite_m2s_a_sz(addr_width),
137 full_throughput => full_throughput,
138 allow_poor_input_ready_timing => allow_poor_input_ready_timing
139 )
140 port map(
141 clk => clk,
142 --
143 input_ready => master_s2m.read.ar.ready,
144 input_valid => master_m2s.read.ar.valid,
145 input_data => input_data,
146 --
147 output_ready => slave_s2m.read.ar.ready,
148 output_valid => slave_m2s.read.ar.valid,
149 output_data => output_data
150 );
151 end block;
152
153
154 ------------------------------------------------------------------------------
155 r_block : block
156 2 constant r_width : integer := axi_lite_s2m_r_sz(data_width);
157 140 signal master_s2m_r, slave_s2m_r : std_logic_vector(r_width - 1 downto 0);
158 begin
159
160
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270320 master_s2m.read.r.data <= to_axi_lite_s2m_r(master_s2m_r, data_width).data;
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6260 master_s2m.read.r.resp <= to_axi_lite_s2m_r(master_s2m_r, data_width).resp;
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152942 slave_s2m_r <= to_slv(slave_s2m.read.r, data_width);
163
164 4 handshake_pipeline_inst : entity common.handshake_pipeline
165 generic map (
166 data_width => r_width,
167 full_throughput => full_throughput,
168 allow_poor_input_ready_timing => allow_poor_input_ready_timing
169 )
170 port map(
171 clk => clk,
172 --
173 input_ready => slave_m2s.read.r.ready,
174 input_valid => slave_s2m.read.r.valid,
175 input_data => slave_s2m_r,
176 --
177 output_ready => master_m2s.read.r.ready,
178 output_valid => master_s2m.read.r.valid,
179 output_data => master_s2m_r
180 );
181 end block;
182
183 end architecture;
184