tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_lite_pkg.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 65 65 100.0%
Branches: 112 203 55.2%

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380528 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Data types for working with AXI4-Lite interfaces.
9 -- Based on the document "ARM IHI 0022E (ID022613): AMBA AXI and ACE Protocol Specification"
10 -- Available here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/
11 -- -------------------------------------------------------------------------------------------------
12
13 library ieee;
14 use ieee.std_logic_1164.all;
15 use ieee.numeric_std.all;
16
17 use work.axi_pkg.all;
18
19
20 package axi_lite_pkg is
21
22 ------------------------------------------------------------------------------
23 -- A (Address Read and Address Write) channels
24 ------------------------------------------------------------------------------
25
26 type axi_lite_m2s_a_t is record
27 valid : std_logic;
28 addr : unsigned(axi_a_addr_sz - 1 downto 0);
29 -- Excluded members: prot
30 -- These are typically not changed on a transfer-to-transfer basis.
31 end record;
32
33
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5200 constant axi_lite_m2s_a_init : axi_lite_m2s_a_t := (valid => '0', others => (others => '0'));
34 function axi_lite_m2s_a_sz(addr_width : positive) return positive;
35
36 type axi_lite_s2m_a_t is record
37 ready : std_logic;
38 end record;
39
40 80 constant axi_lite_s2m_a_init : axi_lite_s2m_a_t := (ready => '0');
41
42
43 ------------------------------------------------------------------------------
44 -- W (Write Data) channels
45 ------------------------------------------------------------------------------
46
47 -- Max values
48 80 constant axi_lite_data_sz : positive := 64;
49 80 constant axi_lite_w_strb_sz : positive := axi_lite_data_sz / 8;
50
51 function to_axi_lite_strb(data_width : positive) return std_logic_vector;
52
53 type axi_lite_m2s_w_t is record
54 valid : std_logic;
55 data : std_logic_vector(axi_lite_data_sz - 1 downto 0);
56 strb : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0);
57 end record;
58
59
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5840 constant axi_lite_m2s_w_init : axi_lite_m2s_w_t := (valid => '0', others => (others => '-'));
60
61 function axi_lite_m2s_w_sz(data_width : positive) return positive;
62 function to_slv(data : axi_lite_m2s_w_t; data_width : positive) return std_logic_vector;
63 function to_axi_lite_m2s_w(data : std_logic_vector; data_width : positive) return axi_lite_m2s_w_t;
64
65 type axi_lite_s2m_w_t is record
66 ready : std_logic;
67 end record;
68
69 80 constant axi_lite_s2m_w_init : axi_lite_s2m_w_t := (ready => '0');
70
71
72 ------------------------------------------------------------------------------
73 -- B (Write Response) channels
74 ------------------------------------------------------------------------------
75
76 type axi_lite_m2s_b_t is record
77 ready : std_logic;
78 end record;
79
80 80 constant axi_lite_m2s_b_init : axi_lite_m2s_b_t := (ready => '0');
81
82 type axi_lite_s2m_b_t is record
83 valid : std_logic;
84 resp : std_logic_vector(axi_resp_sz - 1 downto 0);
85 end record;
86
87
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240 constant axi_lite_s2m_b_init : axi_lite_s2m_b_t := (valid => '0', others => (others => '0'));
88 -- Exluded member: valid
89 80 constant axi_lite_s2m_b_sz : positive := axi_resp_sz;
90
91
92 ------------------------------------------------------------------------------
93 -- R (Read Data) channels
94 ------------------------------------------------------------------------------
95
96 type axi_lite_m2s_r_t is record
97 ready : std_logic;
98 end record;
99
100 80 constant axi_lite_m2s_r_init : axi_lite_m2s_r_t := (ready => '0');
101
102 type axi_lite_s2m_r_t is record
103 valid : std_logic;
104 data : std_logic_vector(axi_lite_data_sz - 1 downto 0);
105 resp : std_logic_vector(axi_resp_sz - 1 downto 0);
106 end record;
107
108
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5360 constant axi_lite_s2m_r_init : axi_lite_s2m_r_t := (valid => '0', others => (others => '0'));
109 function axi_lite_s2m_r_sz(data_width : positive) return positive;
110 function to_slv(data : axi_lite_s2m_r_t; data_width : positive) return std_logic_vector;
111 function to_axi_lite_s2m_r(data : std_logic_vector; data_width : positive) return axi_lite_s2m_r_t;
112
113
114 ------------------------------------------------------------------------------
115 -- The complete buses
116 ------------------------------------------------------------------------------
117
118 type axi_lite_read_m2s_t is record
119 ar : axi_lite_m2s_a_t;
120 r : axi_lite_m2s_r_t;
121 end record;
122 type axi_lite_read_m2s_vec_t is array (integer range <>) of axi_lite_read_m2s_t;
123
124 80 constant axi_lite_read_m2s_init : axi_lite_read_m2s_t := (
125 ar => axi_lite_m2s_a_init,
126 r => axi_lite_m2s_r_init
127 );
128
129 type axi_lite_read_s2m_t is record
130 ar : axi_lite_s2m_a_t;
131 r : axi_lite_s2m_r_t;
132 end record;
133 type axi_lite_read_s2m_vec_t is array (integer range <>) of axi_lite_read_s2m_t;
134
135 80 constant axi_lite_read_s2m_init : axi_lite_read_s2m_t := (
136 ar => axi_lite_s2m_a_init,
137 r => axi_lite_s2m_r_init
138 );
139
140 type axi_lite_write_m2s_t is record
141 aw : axi_lite_m2s_a_t;
142 w : axi_lite_m2s_w_t;
143 b : axi_lite_m2s_b_t;
144 end record;
145 type axi_lite_write_m2s_vec_t is array (integer range <>) of axi_lite_write_m2s_t;
146
147 80 constant axi_lite_write_m2s_init : axi_lite_write_m2s_t := (
148 aw => axi_lite_m2s_a_init,
149 w => axi_lite_m2s_w_init,
150 b => axi_lite_m2s_b_init
151 );
152
153 type axi_lite_write_s2m_t is record
154 aw : axi_lite_s2m_a_t;
155 w : axi_lite_s2m_w_t;
156 b : axi_lite_s2m_b_t;
157 end record;
158 type axi_lite_write_s2m_vec_t is array (integer range <>) of axi_lite_write_s2m_t;
159
160 80 constant axi_lite_write_s2m_init : axi_lite_write_s2m_t := (
161 aw => axi_lite_s2m_a_init,
162 w => axi_lite_s2m_w_init,
163 b => axi_lite_s2m_b_init
164 );
165
166 type axi_lite_m2s_t is record
167 read : axi_lite_read_m2s_t;
168 write : axi_lite_write_m2s_t;
169 end record;
170 type axi_lite_m2s_vec_t is array (integer range <>) of axi_lite_m2s_t;
171
172 80 constant axi_lite_m2s_init : axi_lite_m2s_t := (
173 read => axi_lite_read_m2s_init,
174 write => axi_lite_write_m2s_init
175 );
176
177 type axi_lite_s2m_t is record
178 read : axi_lite_read_s2m_t;
179 write : axi_lite_write_s2m_t;
180 end record;
181 type axi_lite_s2m_vec_t is array (integer range <>) of axi_lite_s2m_t;
182
183 80 constant axi_lite_s2m_init : axi_lite_s2m_t := (
184 read => axi_lite_read_s2m_init,
185 write => axi_lite_write_s2m_init
186 );
187
188 end;
189
190 package body axi_lite_pkg is
191
192 function axi_lite_m2s_a_sz(addr_width : positive) return positive is
193 begin
194 -- Excluded membed: valid.
195 16092 return addr_width;
196 end function;
197
198 function axi_lite_m2s_w_sz(data_width : positive) return positive is
199 begin
200
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73946 assert data_width = 32 or data_width = 64
201 report "AXI4-Lite protocol only supports data width 32 or 64" severity failure;
202 -- Exluded member: valid
203
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73946 return data_width + axi_w_strb_width(data_width);
204 end function;
205
206 function to_axi_lite_strb(data_width : positive) return std_logic_vector is
207
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36 variable result : std_logic_vector(axi_lite_w_strb_sz - 1 downto 0) := (others => '0');
208 begin
209
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28 result(data_width / 8 - 1 downto 0) := (others => '1');
210 4 return result;
211 end function;
212
213 function to_slv(data : axi_lite_m2s_w_t; data_width : positive) return std_logic_vector is
214
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2286148 variable result : std_logic_vector(axi_lite_m2s_w_sz(data_width) - 1 downto 0);
215 57892 variable lo, hi : natural := 0;
216 begin
217 57892 lo := 0;
218
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57892 hi := lo + data_width - 1;
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57892 result(hi downto lo) := data.data(data_width - 1 downto 0);
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57892 lo := hi + 1;
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57892 hi := lo + axi_w_strb_width(data_width) - 1;
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57892 result(hi downto lo) := data.strb(axi_w_strb_width(data_width) - 1 downto 0);
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57892 assert hi = result'high severity failure;
224 57892 return result;
225 end function;
226
227 function to_axi_lite_m2s_w(
228 data : std_logic_vector;
229 data_width : positive
230 ) return axi_lite_m2s_w_t is
231 66084 variable result : axi_lite_m2s_w_t := axi_lite_m2s_w_init;
232 66084 variable lo, hi : natural := 0;
233 begin
234 66084 lo := 0;
235
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66084 hi := lo + data_width - 1;
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66084 result.data(data_width - 1 downto 0) := data(hi downto lo);
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66084 lo := hi + 1;
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66084 hi := lo + axi_w_strb_width(data_width) - 1;
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66084 result.strb(axi_w_strb_width(data_width) - 1 downto 0) := data(hi downto lo);
240
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66084 assert hi = data'high severity failure;
241 66084 return result;
242 end function;
243
244 function axi_lite_s2m_r_sz(data_width : positive) return positive is
245 begin
246 -- Exluded member: valid
247
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57856 return data_width + axi_resp_sz;
248 end function;
249
250 function to_slv(data : axi_lite_s2m_r_t; data_width : positive) return std_logic_vector is
251
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1591198 variable result : std_logic_vector(axi_lite_s2m_r_sz(data_width) - 1 downto 0);
252 41802 variable lo, hi : natural := 0;
253 begin
254 41802 lo := 0;
255
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41802 hi := lo + data_width - 1;
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41802 result(hi downto lo) := data.data(data_width - 1 downto 0);
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41802 lo := hi + 1;
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41802 hi := lo + axi_resp_sz - 1;
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41802 result(hi downto lo) := data.resp;
260
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41802 assert hi = result'high severity failure;
261 41802 return result;
262 end function;
263
264 function to_axi_lite_s2m_r(
265 data : std_logic_vector;
266 data_width : positive
267 ) return axi_lite_s2m_r_t is
268 66380 variable result : axi_lite_s2m_r_t := axi_lite_s2m_r_init;
269 66380 variable lo, hi : natural := 0;
270 begin
271 66380 lo := 0;
272
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66380 hi := lo + data_width - 1;
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66380 result.data(data_width - 1 downto 0) := data(hi downto lo);
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66380 lo := hi + 1;
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66380 hi := lo + axi_resp_sz - 1;
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66380 result.resp := data(hi downto lo);
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66380 assert hi = data'high severity failure;
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66460 return result;
279 end function;
280
281 end;
282