tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_lite_read_slave.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 120 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library axi;
16 use axi.axi_pkg.all;
17 use axi.axi_lite_pkg.all;
18
19 library vunit_lib;
20 context vunit_lib.vc_context;
21
22
23
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5380 entity axi_lite_read_slave is
24 generic (
25
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180 axi_slave : axi_slave_t;
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1300 data_width : integer
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340 );
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140 port (
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100 clk : in std_logic;
30 --
31 20 axi_lite_read_m2s : in axi_lite_read_m2s_t := axi_lite_read_m2s_init;
32 20 axi_lite_read_s2m : out axi_lite_read_s2m_t := axi_lite_read_s2m_init
33
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1364 end entity;
35 100
36 20 architecture a of axi_lite_read_slave is
37
38 20 constant len : std_logic_vector(axi_a_len_sz - 1 downto 0) := std_logic_vector(to_len(1));
39 20 constant size : std_logic_vector(axi_a_size_sz - 1 downto 0) :=
40 std_logic_vector(to_size(data_width));
41
42 -- Using "open" not ok in GHDL: unconstrained port "rid" must be connected
43 660 signal rid, aid : std_logic_vector(8 - 1 downto 0) := (others => '0');
44
45 1320 signal araddr : std_logic_vector(axi_lite_read_m2s.ar.addr'range);
46
47 begin
48
49 ------------------------------------------------------------------------------
50 37812 axi_read_slave_inst : entity vunit_lib.axi_read_slave
51 generic map (
52 axi_slave => axi_slave
53 )
54 port map (
55 aclk => clk,
56
57 arvalid => axi_lite_read_m2s.ar.valid,
58 arready => axi_lite_read_s2m.ar.ready,
59 arid => aid,
60 araddr => araddr,
61 arlen => len,
62 arsize => size,
63 arburst => axi_a_burst_fixed,
64
65 rvalid => axi_lite_read_s2m.r.valid,
66 rready => axi_lite_read_m2s.r.ready,
67 rid => rid,
68 rdata => axi_lite_read_s2m.r.data(data_width - 1 downto 0),
69 rresp => axi_lite_read_s2m.r.resp,
70 rlast => open
71 );
72
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2457780 araddr <= std_logic_vector(axi_lite_read_m2s.ar.addr);
74
75 end architecture;
76