tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/reg_file/axi_lite_reg_file_wrapper.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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Branches: 0 90 0.0%

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1 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper, for netlist build and formal flow, that sets an appropriate generic.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library axi;
15 use axi.axi_lite_pkg.all;
16
17 -- TODO there is some problem in our formal flow related to the work library.
18 -- Doing simply "use work.reg_file_pkg.all;" does not work here. The issue seems to be
19 -- isolated to the top level however, since axi_lite_reg_file.vhd uses "work" completely fine.
20 --
21 -- Appending "--work=reg_file" in the sby_writer.py ghdl elaborate call did not immediately solve
22 -- the issue.
23 library reg_file;
24 use reg_file.reg_file_pkg.all;
25
26
27 entity axi_lite_reg_file_wrapper is
28 port (
29 clk : in std_logic;
30 --
31 axi_lite_m2s : in axi_lite_m2s_t;
32 axi_lite_s2m : out axi_lite_s2m_t;
33 --
34 regs_up : in reg_vec_t(0 to 15 - 1);
35 regs_down : out reg_vec_t(0 to 15 - 1);
36 --
37 reg_was_read : out std_logic_vector(0 to 15 - 1);
38 reg_was_written : out std_logic_vector(0 to 15 - 1)
39 );
40 end entity;
41
42 architecture a of axi_lite_reg_file_wrapper is
43
44 constant regs : reg_definition_vec_t(regs_up'range) := (
45 (idx=>0, reg_type=>r),
46 (idx=>1, reg_type=>w),
47 (idx=>2, reg_type=>r_w),
48 (idx=>3, reg_type=>wpulse),
49 (idx=>4, reg_type=>r_wpulse),
50 (idx=>5, reg_type=>r),
51 (idx=>6, reg_type=>w),
52 (idx=>7, reg_type=>r_w),
53 (idx=>8, reg_type=>wpulse),
54 (idx=>9, reg_type=>r_wpulse),
55 (idx=>10, reg_type=>r),
56 (idx=>11, reg_type=>w),
57 (idx=>12, reg_type=>r_w),
58 (idx=>13, reg_type=>wpulse),
59 (idx=>14, reg_type=>r_wpulse)
60 );
61
62 begin
63
64 axi_lite_reg_file_inst : entity reg_file.axi_lite_reg_file
65 generic map (
66 regs => regs
67 )
68 port map (
69 clk => clk,
70 --
71 axi_lite_m2s => axi_lite_m2s,
72 axi_lite_s2m => axi_lite_s2m,
73 --
74 regs_up => regs_up,
75 regs_down => regs_down,
76 --
77 reg_was_read => reg_was_read,
78 reg_was_written => reg_was_written
79 );
80
81 end architecture;
82