tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_lite_simple_read_crossbar.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 26 26 100.0%
Branches: 135 168 80.4%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Simple N-to-1 crossbar for connecting multiple AXI-Lite masters to one port.
9 -- This is a wrapper around the simple AXI read crossbar. See that entity for details.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14
15 library axi;
16 use axi.axi_pkg.all;
17 use axi.axi_lite_pkg.all;
18
19
20
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4656 entity axi_lite_simple_read_crossbar is
21 generic(
22 num_inputs : integer
23 );
24 port(
25 clk : in std_logic;
26 --
27 input_ports_m2s : in axi_lite_read_m2s_vec_t(0 to num_inputs - 1) :=
28 (others => axi_lite_read_m2s_init);
29 input_ports_s2m : out axi_lite_read_s2m_vec_t(0 to num_inputs - 1) :=
30 (others => axi_lite_read_s2m_init);
31 --
32 output_m2s : out axi_lite_read_m2s_t := axi_lite_read_m2s_init;
33 output_s2m : in axi_lite_read_s2m_t := axi_lite_read_s2m_init
34 );
35 end entity;
36
37 12 architecture a of axi_lite_simple_read_crossbar is
38
39
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1652 signal input_ports_axi_m2s : axi_read_m2s_vec_t(0 to num_inputs - 1) :=
40
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2490 (others => axi_read_m2s_init);
41 1250 signal input_ports_axi_s2m : axi_read_s2m_vec_t(0 to num_inputs - 1) :=
42
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406 (others => axi_read_s2m_init);
43 310
44 204 signal output_axi_m2s : axi_read_m2s_t := axi_read_m2s_init;
45 318 signal output_axi_s2m : axi_read_s2m_t := axi_read_s2m_init;
46
47 begin
48
49 -- Assign to the AXI records only what is needed for the AXI-Lite function.
50
51 ------------------------------------------------------------------------------
52 input_ports_loop : for input_idx in input_ports_m2s'range generate
53 2040 input_ports_axi_m2s(input_idx).ar.valid <= input_ports_m2s(input_idx).ar.valid;
54
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1812 input_ports_axi_m2s(input_idx).ar.addr <= input_ports_m2s(input_idx).ar.addr;
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9328 input_ports_s2m(input_idx).ar.ready <= input_ports_axi_s2m(input_idx).ar.ready;
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2016 input_ports_axi_m2s(input_idx).r.ready <= input_ports_m2s(input_idx).r.ready;
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2016 input_ports_s2m(input_idx).r.valid <= input_ports_axi_s2m(input_idx).r.valid;
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2852 input_ports_s2m(input_idx).r.data <=
62 input_ports_axi_s2m(input_idx).r.data(input_ports_s2m(input_idx).r.data'range);
63
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114 input_ports_s2m(input_idx).r.resp <=
64 input_ports_axi_s2m(input_idx).r.resp(input_ports_s2m(input_idx).r.resp'range);
65 end generate;
66
67
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2004 output_m2s.ar.valid <= output_axi_m2s.ar.valid;
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130518 output_m2s.ar.addr <= output_axi_m2s.ar.addr;
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33170 output_axi_s2m.ar.ready <= output_s2m.ar.ready;
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2004 output_m2s.r.ready <= output_axi_m2s.r.ready;
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2004 output_axi_s2m.r.valid <= output_s2m.r.valid;
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583 output_axi_s2m.r.data(output_s2m.r.data'range) <= output_s2m.r.data;
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22 output_axi_s2m.r.resp(output_s2m.r.resp'range) <= output_s2m.r.resp;
77 -- AXI-Lite always burst length 1. Need to set last for the logic in axi_interconnect.
78
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4 output_axi_s2m.r.last <= '1';
79
80
81 ------------------------------------------------------------------------------
82
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4 axi_simple_read_crossbar_inst : entity work.axi_simple_read_crossbar
83 generic map (
84 num_inputs => num_inputs
85 )
86 port map (
87 clk => clk,
88 --
89 input_ports_m2s => input_ports_axi_m2s,
90 input_ports_s2m => input_ports_axi_s2m,
91 --
92 output_m2s => output_axi_m2s,
93 output_s2m => output_axi_s2m
94 );
95
96 end architecture;
97