tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_lite_slave.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 120 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- Will instantiate read and/or write BFMs based on what generics are provided.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14 use ieee.numeric_std.all;
15
16 library vunit_lib;
17 context vunit_lib.vc_context;
18
19 library axi;
20 use axi.axi_pkg.all;
21 use axi.axi_lite_pkg.all;
22
23 use work.axi_slave_pkg.all;
24
25
26
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10880 entity axi_lite_slave is
27 generic (
28 axi_read_slave : axi_slave_t := axi_slave_init;
29 40 axi_write_slave : axi_slave_t := axi_slave_init;
30 data_width : integer
31
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4040 );
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2760 port (
33 clk : in std_logic;
34 --
35 axi_lite_read_m2s : in axi_lite_read_m2s_t := axi_lite_read_m2s_init;
36 axi_lite_read_s2m : out axi_lite_read_s2m_t := axi_lite_read_s2m_init;
37 --
38 axi_lite_write_m2s : in axi_lite_write_m2s_t := axi_lite_write_m2s_init;
39 axi_lite_write_s2m : out axi_lite_write_s2m_t := axi_lite_write_s2m_init
40 );
41 end entity;
42
43 40 architecture a of axi_lite_slave is
44
45 begin
46
47 ------------------------------------------------------------------------------
48 axi_read_slave_gen : if axi_read_slave /= axi_slave_init generate
49
50 40 axi_lite_read_slave_inst : entity work.axi_lite_read_slave
51 generic map (
52 axi_slave => axi_read_slave,
53 data_width => data_width
54 )
55 port map (
56 clk => clk,
57 --
58 axi_lite_read_m2s => axi_lite_read_m2s,
59 axi_lite_read_s2m => axi_lite_read_s2m
60 );
61 end generate;
62
63
64 ------------------------------------------------------------------------------
65 axi_write_slave_gen : if axi_write_slave /= axi_slave_init generate
66
67 80 axi_lite_write_slave_inst : entity work.axi_lite_write_slave
68 generic map (
69 axi_slave => axi_write_slave,
70 data_width => data_width
71 )
72 port map (
73 clk => clk,
74 --
75 axi_lite_write_m2s => axi_lite_write_m2s,
76 axi_lite_write_s2m => axi_lite_write_s2m
77 );
78
79 end generate;
80
81
82 end architecture;
83