tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_lite_to_vec.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 48 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Convenience wrapper for splitting and CDC'ing a register bus.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library axi;
15 use axi.axi_lite_pkg.all;
16
17 library common;
18 use common.addr_pkg.all;
19 use common.attribute_pkg.all;
20
21 library reg_file;
22 use reg_file.reg_file_pkg.all;
23
24
25
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23864 entity axi_lite_to_vec is
26 generic (
27 axi_lite_slaves : addr_and_mask_vec_t;
28 clocks_are_the_same : boolean_vector(axi_lite_slaves'range) := (others => true);
29 cdc_fifo_depth : positive := 16;
30 cdc_ram_type : ram_style_t := ram_style_auto
31 );
32 14 port (
33
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2814 clk_axi_lite : in std_logic;
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1918 axi_lite_m2s : in axi_lite_m2s_t;
35 axi_lite_s2m : out axi_lite_s2m_t;
36 14
37
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5614 -- Only need to set if different from clk_axi_lite
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966 clk_axi_lite_vec : in std_logic_vector(axi_lite_slaves'range) := (others => '0');
39 8 axi_lite_m2s_vec : out axi_lite_m2s_vec_t(axi_lite_slaves'range);
40 axi_lite_s2m_vec : in axi_lite_s2m_vec_t(axi_lite_slaves'range)
41
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1608 );
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1096 end entity;
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14560 architecture a of axi_lite_to_vec is
45 2492
46 8 constant addr_width : positive := addr_bits_needed(axi_lite_slaves);
47
48 7244 signal axi_lite_m2s_vec_int : axi_lite_m2s_vec_t(axi_lite_slaves'range);
49 2528 signal axi_lite_s2m_vec_int : axi_lite_s2m_vec_t(axi_lite_slaves'range);
50
51 begin
52
53 ------------------------------------------------------------------------------
54
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1652 axi_lite_mux_inst : entity axi.axi_lite_mux
55 generic map (
56 slave_addrs => axi_lite_slaves
57 )
58 port map (
59 clk => clk_axi_lite,
60
61 axi_lite_m2s => axi_lite_m2s,
62 axi_lite_s2m => axi_lite_s2m,
63
64 axi_lite_m2s_vec => axi_lite_m2s_vec_int,
65 axi_lite_s2m_vec => axi_lite_s2m_vec_int
66 );
67
68
69 ------------------------------------------------------------------------------
70 clock_domain_crossing : for slave in axi_lite_slaves'range generate
71 36 assign : if clocks_are_the_same(slave) generate
72
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357274 axi_lite_m2s_vec(slave) <= axi_lite_m2s_vec_int(slave);
73 axi_lite_s2m_vec_int(slave) <= axi_lite_s2m_vec(slave);
74
75 else generate
76
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74 axi_lite_cdc_inst : entity axi.axi_lite_cdc
77 generic map (
78 data_width => reg_width,
79 addr_width => addr_width,
80 fifo_depth => cdc_fifo_depth,
81 ram_type => cdc_ram_type
82 )
83 port map (
84 clk_master => clk_axi_lite,
85 master_m2s => axi_lite_m2s_vec_int(slave),
86 master_s2m => axi_lite_s2m_vec_int(slave),
87 --
88 clk_slave => clk_axi_lite_vec(slave),
89 slave_m2s => axi_lite_m2s_vec(slave),
90 slave_s2m => axi_lite_s2m_vec(slave)
91 );
92 end generate;
93 end generate;
94
95 end architecture;
96