tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_lite_write_slave.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 126 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library axi;
16 use axi.axi_pkg.all;
17 use axi.axi_lite_pkg.all;
18
19 library vunit_lib;
20 context vunit_lib.vc_context;
21
22
23
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5964 entity axi_lite_write_slave is
24 generic (
25 axi_slave : axi_slave_t;
26 21 data_width : integer
27 21 );
28
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189 port (
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1365 clk : in std_logic;
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357 --
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147 axi_lite_write_m2s : in axi_lite_write_m2s_t := axi_lite_write_m2s_init;
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105 axi_lite_write_s2m : out axi_lite_write_s2m_t := axi_lite_write_s2m_init
33 );
34 21 end entity;
35 21
36
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725 architecture a of axi_lite_write_slave is
37 189
38 42 constant len : std_logic_vector(axi_a_len_sz - 1 downto 0) := std_logic_vector(to_len(1));
39 21 constant size : std_logic_vector(axi_a_size_sz - 1 downto 0) :=
40 21 std_logic_vector(to_size(data_width));
41 21
42
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357 -- Using "open" not ok in GHDL: unconstrained port "rid" must be connected
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798 signal bid, aid : std_logic_vector(8 - 1 downto 0) := (others => '0');
44
45 1386 signal awaddr : std_logic_vector(axi_lite_write_m2s.aw.addr'range);
46
47 begin
48
49 ------------------------------------------------------------------------------
50 41912 axi_write_slave_inst : entity vunit_lib.axi_write_slave
51 generic map (
52 axi_slave => axi_slave
53 )
54 port map (
55 aclk => clk,
56 --
57 awvalid => axi_lite_write_m2s.aw.valid,
58 awready => axi_lite_write_s2m.aw.ready,
59 awid => aid,
60 awaddr => awaddr,
61 awlen => len,
62 awsize => size,
63 awburst => axi_a_burst_fixed,
64 --
65 wvalid => axi_lite_write_m2s.w.valid,
66 wready => axi_lite_write_s2m.w.ready,
67 wdata => axi_lite_write_m2s.w.data(data_width - 1 downto 0),
68 wstrb => axi_lite_write_m2s.w.strb,
69 wlast => '1',
70 --
71 bvalid => axi_lite_write_s2m.b.valid,
72 bready => axi_lite_write_m2s.b.ready,
73 bid => bid,
74 bresp => axi_lite_write_s2m.b.resp
75 );
76
77
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2724280 awaddr <= std_logic_vector(axi_lite_write_m2s.aw.addr);
78
79 end architecture;
80