tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_master.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 180 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 use ieee.numeric_std.all;
12
13 library math;
14 use math.math_pkg.all;
15
16 library axi;
17 use axi.axi_pkg.all;
18
19 library vunit_lib;
20 context vunit_lib.vunit_context;
21 context vunit_lib.vc_context;
22
23
24
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41415 entity axi_master is
25 generic (
26 30 bus_handle : bus_master_t
27 );
28 30 port (
29 30 clk : in std_logic;
30 5022
31 axi_read_m2s : out axi_read_m2s_t := axi_read_m2s_init;
32 30 axi_read_s2m : in axi_read_s2m_t := axi_read_s2m_init;
33 30
34
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1022 axi_write_m2s : out axi_write_m2s_t := axi_write_m2s_init;
35
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90 axi_write_s2m : in axi_write_s2m_t := axi_write_s2m_init
36 );
37 30 end entity;
38 30
39
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5022 architecture a of axi_master is
40
41 60 constant data_width : positive := data_length(bus_handle);
42 30
43
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3036 constant len : unsigned(axi_write_m2s.aw.len'range) := to_len(1);
44
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432 constant size : unsigned(axi_write_m2s.aw.size'range) := to_size(data_width);
45
46 3388 signal araddr, awaddr : std_logic_vector(address_length(bus_handle) - 1 downto 0);
47 2044 signal rdata, wdata : std_logic_vector(data_width - 1 downto 0);
48
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274 signal wstrb : std_logic_vector(byte_enable_length(bus_handle) - 1 downto 0);
49
50 begin
51
52 ------------------------------------------------------------------------------
53 529739 axi_read_m2s.ar.addr(araddr'range) <= unsigned(araddr);
54
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540 axi_read_m2s.ar.len <= len;
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240 axi_read_m2s.ar.size <= size;
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180 axi_read_m2s.ar.burst <= axi_a_burst_incr;
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58
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472845 rdata <= axi_read_s2m.r.data(rdata'range);
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60
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592239 axi_write_m2s.aw.addr(awaddr'range) <= unsigned(awaddr);
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540 axi_write_m2s.aw.len <= len;
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240 axi_write_m2s.aw.size <= size;
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180 axi_write_m2s.aw.burst <= axi_a_burst_incr;
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333026 axi_write_m2s.w.data(wdata'range) <= wdata;
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60 axi_write_m2s.w.last <= '1';
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516 axi_write_m2s.w.strb(wstrb'range) <= wstrb;
68
69
70 ------------------------------------------------------------------------------
71 60 axi_lite_master_inst : entity vunit_lib.axi_lite_master
72 generic map (
73 bus_handle => bus_handle
74 )
75 port map (
76 aclk => clk,
77
78 arready => axi_read_s2m.ar.ready,
79 arvalid => axi_read_m2s.ar.valid,
80 araddr => araddr,
81
82 rready => axi_read_m2s.r.ready,
83 rvalid => axi_read_s2m.r.valid,
84 rdata => rdata,
85 rresp => axi_read_s2m.r.resp,
86
87 awready => axi_write_s2m.aw.ready,
88 awvalid => axi_write_m2s.aw.valid,
89 awaddr => awaddr,
90
91 wready => axi_write_s2m.w.ready,
92 wvalid => axi_write_m2s.w.valid,
93 wdata => wdata,
94 wstrb => wstrb,
95
96 bready => axi_write_m2s.b.ready,
97 bvalid => axi_write_s2m.b.valid,
98 bresp => axi_write_s2m.b.resp
99 );
100
101 end architecture;
102