tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_r_fifo.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 72 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- FIFO for AXI read response channel (R). Can be used as clock crossing by setting
9 -- the "asynchronous" generic.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14
15 library common;
16 use common.attribute_pkg.all;
17
18 library fifo;
19
20 use work.axi_pkg.all;
21
22
23
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9490 entity axi_r_fifo is
24 generic (
25 asynchronous : boolean;
26 id_width : natural;
27 data_width : positive;
28 depth : natural := 16;
29 enable_packet_mode : boolean := false;
30 ram_type : ram_style_t := ram_style_auto
31 );
32 port (
33 clk : in std_logic;
34 --
35 input_m2s : in axi_m2s_r_t;
36 10 input_s2m : out axi_s2m_r_t := axi_s2m_r_init;
37 --
38 10 output_m2s : out axi_m2s_r_t := axi_m2s_r_init;
39 10 output_s2m : in axi_s2m_r_t;
40 -- Level of the FIFO. If this is an asynchronous FIFO, this value is on the "output" side.
41 10 output_level : out integer range 0 to depth := 0;
42 10 --
43
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1210 -- Only need to assign the clock if generic asynchronous is "True"
44 10 clk_input : in std_logic := '0'
45 );
46 end entity;
47 10
48 24 architecture a of axi_r_fifo is
49 10
50 begin
51 10
52 10 passthrough_or_fifo : if depth = 0 generate
53
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2426 output_m2s <= input_m2s;
54
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311558 input_s2m <= output_s2m;
55
56 else generate
57 10
58 10 constant r_width : integer := axi_s2m_r_sz(data_width, id_width);
59 10
60 10 signal read_valid : std_logic := '0';
61 822 signal read_data, write_data : std_logic_vector(r_width - 1 downto 0);
62 10
63 begin
64
65 ------------------------------------------------------------------------------
66 3890 assign : process(all)
67 begin
68
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4656665 input_s2m <= to_axi_s2m_r(read_data, data_width, id_width);
69
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30043 input_s2m.valid <= read_valid;
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71
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1231763 write_data <= to_slv(output_s2m, data_width, id_width);
72 end process;
73
74
75 ------------------------------------------------------------------------------
76
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22 fifo_wrapper_inst : entity fifo.fifo_wrapper
77 generic map (
78 use_asynchronous_fifo => asynchronous,
79 width => r_width,
80 depth => depth,
81 enable_last => enable_packet_mode,
82 enable_packet_mode => enable_packet_mode,
83 ram_type => ram_type
84 )
85 port map(
86 clk => clk,
87 clk_read => clk_input,
88 clk_write => clk,
89 --
90 read_ready => input_m2s.ready,
91 read_valid => read_valid,
92 read_data => read_data,
93 --
94 write_ready => output_m2s.ready,
95 write_valid => output_s2m.valid,
96 write_data => write_data,
97 --
98 write_level => output_level
99 );
100
101
102 end generate;
103
104 end architecture;
105