tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_read_cdc.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Clock domain crossing for an AXI read bus.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library common;
15 use common.attribute_pkg.all;
16
17 library fifo;
18
19 use work.axi_pkg.all;
20
21
22
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6168 entity axi_read_cdc is
23 generic (
24 id_width : natural;
25 addr_width : positive;
26 data_width : positive;
27 enable_data_fifo_packet_mode : boolean;
28 address_fifo_depth : positive;
29 address_fifo_ram_type : ram_style_t := ram_style_auto;
30 data_fifo_depth : positive;
31 data_fifo_ram_type : ram_style_t := ram_style_auto
32 6 );
33 6 port (
34
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612 clk_input : in std_logic;
35 6 input_m2s : in axi_read_m2s_t;
36
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1854 input_s2m : out axi_read_s2m_t := axi_read_s2m_init;
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1218 --
38 6 clk_output : in std_logic;
39
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930 output_m2s : out axi_read_m2s_t := axi_read_m2s_init;
40 6 output_s2m : in axi_read_s2m_t;
41
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6 output_data_fifo_level : out integer range 0 to data_fifo_depth := 0
42 );
43 end entity;
44 6
45 12 architecture a of axi_read_cdc is
46
47 begin
48
49 ------------------------------------------------------------------------------
50
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6 axi_address_inst : entity work.axi_address_fifo
51 generic map (
52 id_width => id_width,
53 addr_width => addr_width,
54 asynchronous => true,
55 depth => address_fifo_depth,
56 ram_type => address_fifo_ram_type
57 )
58 port map (
59 clk => clk_output,
60 --
61 input_m2s => input_m2s.ar,
62 input_s2m => input_s2m.ar,
63 --
64 output_m2s => output_m2s.ar,
65 output_s2m => output_s2m.ar,
66 --
67 clk_input => clk_input
68 );
69
70
71 ------------------------------------------------------------------------------
72
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12 axi_r_fifo_inst : entity work.axi_r_fifo
73 generic map (
74 id_width => id_width,
75 data_width => data_width,
76 asynchronous => true,
77 depth => data_fifo_depth,
78 enable_packet_mode => enable_data_fifo_packet_mode,
79 ram_type => data_fifo_ram_type
80 )
81 port map (
82 clk => clk_output,
83 --
84 input_m2s => input_m2s.r,
85 input_s2m => input_s2m.r,
86 --
87 output_m2s => output_m2s.r,
88 output_s2m => output_s2m.r,
89 output_level => output_data_fifo_level,
90 --
91 clk_input => clk_input
92 );
93
94 end architecture;
95