tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_read_slave.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 0 23 0.0%
Branches: 0 166 0.0%

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1 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library vunit_lib;
16 context vunit_lib.vc_context;
17
18 library axi;
19 use axi.axi_pkg.all;
20
21
22 entity axi_read_slave is
23 generic (
24 axi_slave : axi_slave_t;
25 data_width : positive;
26 -- Note that the VUnit BFM creates and integer_vector_ptr of length 2**id_width, so a large
27 -- value for id_width might crash your simulator.
28 id_width : natural := 8
29 );
30 port (
31 clk : in std_logic;
32 axi_read_m2s : in axi_read_m2s_t := axi_read_m2s_init;
33 axi_read_s2m : out axi_read_s2m_t := axi_read_s2m_init
34 );
35 end entity;
36
37 architecture a of axi_read_slave is
38
39 signal arid, rid : std_logic_vector(id_width - 1 downto 0);
40 signal araddr : std_logic_vector(axi_read_m2s.ar.addr'range );
41 signal arlen : std_logic_vector(axi_read_m2s.ar.len'range );
42 signal arsize : std_logic_vector(axi_read_m2s.ar.size'range );
43
44 begin
45
46 ------------------------------------------------------------------------------
47 axi_read_slave_inst : entity vunit_lib.axi_read_slave
48 generic map (
49 axi_slave => axi_slave
50 )
51 port map (
52 aclk => clk,
53
54 arvalid => axi_read_m2s.ar.valid,
55 arready => axi_read_s2m.ar.ready,
56 arid => arid,
57 araddr => araddr,
58 arlen => arlen,
59 arsize => arsize,
60 arburst => axi_read_m2s.ar.burst,
61
62 rvalid => axi_read_s2m.r.valid,
63 rready => axi_read_m2s.r.ready,
64 rid => rid,
65 rdata => axi_read_s2m.r.data(data_width - 1 downto 0),
66 rresp => axi_read_s2m.r.resp,
67 rlast => axi_read_s2m.r.last
68 );
69
70 arid <= std_logic_vector(axi_read_m2s.ar.id(id_width - 1 downto 0));
71 araddr <= std_logic_vector(axi_read_m2s.ar.addr);
72 arlen <= std_logic_vector(axi_read_m2s.ar.len);
73 arsize <= std_logic_vector(axi_read_m2s.ar.size);
74
75 axi_read_s2m.r.id(id_width - 1 downto 0) <= unsigned(rid);
76
77 end architecture;
78