tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_slave.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 96 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- Will instantiate read and/or write BFMs based on what generics are provided.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14 use ieee.numeric_std.all;
15
16 library vunit_lib;
17 context vunit_lib.vc_context;
18
19 library axi;
20 use axi.axi_pkg.all;
21
22 use work.axi_slave_pkg.all;
23
24
25
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17728 entity axi_slave is
26 generic (
27 axi_read_slave : axi_slave_t := axi_slave_init;
28 axi_write_slave : axi_slave_t := axi_slave_init;
29 data_width : positive;
30 -- Note that the VUnit BFM creates and integer_vector_ptr of length 2**id_width, so a large
31 16 -- value for id_width might crash your simulator.
32
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1632 id_width : natural := 8;
33
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9264 w_fifo_depth : natural := 0
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848 );
35 port (
36 clk : in std_logic;
37 --
38 axi_read_m2s : in axi_read_m2s_t := axi_read_m2s_init;
39 axi_read_s2m : out axi_read_s2m_t := axi_read_s2m_init;
40 --
41 axi_write_m2s : in axi_write_m2s_t := axi_write_m2s_init;
42 axi_write_s2m : out axi_write_s2m_t := axi_write_s2m_init
43 );
44 end entity;
45
46 32 architecture a of axi_slave is
47
48 begin
49
50 ------------------------------------------------------------------------------
51 axi_read_slave_gen : if axi_read_slave /= axi_slave_init generate
52
53 32 axi_read_slave_inst : entity work.axi_read_slave
54 generic map (
55 axi_slave => axi_read_slave,
56 data_width => data_width,
57 id_width => id_width
58 )
59 port map (
60 clk => clk,
61 axi_read_m2s => axi_read_m2s,
62 axi_read_s2m => axi_read_s2m
63 );
64
65 end generate;
66
67
68 ------------------------------------------------------------------------------
69 axi_write_slave_gen : if axi_write_slave /= axi_slave_init generate
70
71 64 axi_write_slave_inst : entity work.axi_write_slave
72 generic map (
73 axi_slave => axi_write_slave,
74 data_width => data_width,
75 id_width => id_width,
76 w_fifo_depth => w_fifo_depth
77 )
78 port map (
79 clk => clk,
80 axi_write_m2s => axi_write_m2s,
81 axi_write_s2m => axi_write_s2m
82 );
83
84 end generate;
85
86 end architecture;
87