tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_stream_fifo.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
Lines: 21 21 100.0%
Branches: 41 57 71.9%

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1 12 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- FIFO for AXI Stream. Can be used as clock crossing by setting the "asynchronous" generic.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library fifo;
15
16 library common;
17 use common.attribute_pkg.all;
18
19 use work.axi_stream_pkg.all;
20
21
22
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1174 entity axi_stream_fifo is
23 generic (
24 data_width : positive;
25 user_width : natural;
26 asynchronous : boolean;
27 depth : positive;
28 ram_type : ram_style_t := ram_style_auto
29 );
30 port (
31 clk : in std_logic;
32 --
33 input_m2s : in axi_stream_m2s_t;
34 input_s2m : out axi_stream_s2m_t := axi_stream_s2m_init;
35 --
36 2 output_m2s : out axi_stream_m2s_t := axi_stream_m2s_init;
37 output_s2m : in axi_stream_s2m_t;
38 2 -- Only need to assign the clock if generic asynchronous is "True"
39 2 clk_output : in std_logic := '0'
40 );
41 2 end entity;
42 2
43
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296 architecture a of axi_stream_fifo is
44 2
45 2 constant bus_width : integer := axi_stream_m2s_sz(data_width, user_width);
46
47
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200 signal write_data, read_data : std_logic_vector(bus_width - 1 downto 0);
48 4 signal read_valid : std_logic := '0';
49 2
50 begin
51 2
52 698 write_data <= to_slv(input_m2s, data_width, user_width);
53 100
54
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1550 output_m2s <= to_axi_stream_m2s(
55 data=>read_data,
56 data_width=>data_width,
57
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2 user_width=>user_width,
58 valid=>read_valid
59 2 );
60
61
62 2 ------------------------------------------------------------------------------
63
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4 fifo_wrapper_inst : entity fifo.fifo_wrapper
64 generic map (
65 use_asynchronous_fifo => asynchronous,
66 width => bus_width,
67 depth => depth,
68 ram_type => ram_type
69 )
70 port map(
71 clk => clk,
72 clk_read => clk_output,
73 clk_write => clk,
74 --
75 read_ready => output_s2m.ready,
76 read_valid => read_valid,
77 read_data => read_data,
78 --
79 write_ready => input_s2m.ready,
80 write_valid => input_m2s.valid,
81 write_data => write_data
82 );
83
84 end architecture;
85