tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_to_axi_lite.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 108 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Convert AXI transfers to AXI-Lite transfers.
9 --
10 -- This module does not handle conversion of non-well behaved AXI transfers.
11 -- Burst length has to be one and size must be the width of the bus. If these
12 -- conditions are not met, the read/write response will signal SLVERR.
13 --
14 -- This module will throttle the AXI bus so that there is never more that one
15 -- outstanding transaction (read and write separate). While the AXI-Lite standard
16 -- does allow for outstanding bursts, some Xilinx cores, namely the PCIe DMA bridge
17 -- does not play well with it.
18 -- -------------------------------------------------------------------------------------------------
19
20 library ieee;
21 use ieee.std_logic_1164.all;
22 use ieee.numeric_std.all;
23
24 library common;
25 use common.types_pkg.all;
26
27 library math;
28 use math.math_pkg.all;
29
30 use work.axi_pkg.all;
31 use work.axi_lite_pkg.all;
32
33
34
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36093 entity axi_to_axi_lite is
35 generic (
36 data_width : integer
37 );
38 port (
39 clk : in std_logic;
40
41 axi_m2s : in axi_m2s_t := axi_m2s_init;
42 axi_s2m : out axi_s2m_t := axi_s2m_init;
43
44 axi_lite_m2s : out axi_lite_m2s_t := axi_lite_m2s_init;
45 axi_lite_s2m : in axi_lite_s2m_t := axi_lite_s2m_init
46 );
47 end entity;
48
49 architecture a of axi_to_axi_lite is
50
51 18 constant len : integer := 0;
52 18 constant size : integer := log2(data_width / 8);
53
54 1746 signal read_id, write_id : unsigned(axi_m2s.read.ar.id'range) := (others => '0');
55
56 subtype data_rng is integer range data_width - 1 downto 0;
57 subtype strb_rng is integer range data_width / 8 - 1 downto 0;
58
59 18 signal read_error, write_error : boolean := false;
60
61 36 signal ar_done, aw_done, w_done : std_logic := '0';
62
63 begin
64
65 ------------------------------------------------------------------------------
66 8684 axi_lite_m2s.read.ar.valid <= axi_m2s.read.ar.valid and not ar_done;
67
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143047 axi_lite_m2s.read.ar.addr <= axi_m2s.read.ar.addr;
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31573 axi_s2m.read.ar.ready <= axi_lite_s2m.read.ar.ready and not ar_done;
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4350 axi_lite_m2s.read.r.ready <= axi_m2s.read.r.ready;
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4346 axi_s2m.read.r.valid <= axi_lite_s2m.read.r.valid;
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1532 axi_s2m.read.r.id <= read_id;
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107800 axi_s2m.read.r.data(data_rng) <= axi_lite_s2m.read.r.data(data_rng);
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672 axi_s2m.read.r.resp <= axi_resp_slverr when read_error else axi_lite_s2m.read.r.resp;
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36 axi_s2m.read.r.last <= '1';
78
79
80 ------------------------------------------------------------------------------
81
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6333 axi_lite_m2s.write.aw.valid <= axi_m2s.write.aw.valid and not aw_done;
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138822 axi_lite_m2s.write.aw.addr <= axi_m2s.write.aw.addr;
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31351 axi_s2m.write.aw.ready <= axi_lite_s2m.write.aw.ready and not aw_done;
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6309 axi_lite_m2s.write.w.valid <= axi_m2s.write.w.valid and not w_done;
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101497 axi_lite_m2s.write.w.data(data_rng) <= axi_m2s.write.w.data(data_rng);
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346 axi_lite_m2s.write.w.strb(strb_rng) <= axi_m2s.write.w.strb(strb_rng);
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6317 axi_s2m.write.w.ready <= axi_lite_s2m.write.w.ready and not w_done;
91
92
93 ------------------------------------------------------------------------------
94
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4226 axi_lite_m2s.write.b.ready <= axi_m2s.write.b.ready;
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4226 axi_s2m.write.b.valid <= axi_lite_s2m.write.b.valid;
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1532 axi_s2m.write.b.id <= write_id;
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286104 axi_s2m.write.b.resp <= axi_resp_slverr when write_error else axi_lite_s2m.write.b.resp;
99
100
101 ------------------------------------------------------------------------------
102 882 mirror_id : process
103 begin
104
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285615 wait until rising_edge(clk);
105
106 -- Save the ID's so they can be returned in the read/write response transaction.
107
108
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71403 if axi_s2m.read.ar.ready and axi_m2s.read.ar.valid then
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55625 read_id <= axi_m2s.read.ar.id;
110
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2225 ar_done <= '1';
111 end if;
112
113
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71403 if axi_m2s.read.r.ready and axi_s2m.read.r.valid then
114
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2225 ar_done <= '0';
115 end if;
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71403 if axi_s2m.write.aw.ready and axi_m2s.write.aw.valid then
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53675 write_id <= axi_m2s.write.aw.id;
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2147 aw_done <= '1';
120 end if;
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71403 if axi_s2m.write.w.ready and axi_m2s.write.w.valid then
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2091 w_done <= '1';
124 end if;
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71403 if axi_m2s.write.b.ready and axi_s2m.write.b.valid then
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2147 aw_done <= '0';
128
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428421 w_done <= '0';
129 end if;
130 end process;
131
132
133 ------------------------------------------------------------------------------
134 18 check_for_bus_error : process
135 begin
136
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285615 wait until rising_edge(clk);
137
138 -- If an error occurs the bus will return an error. The bus will be unlocked for any
139 -- upcoming transactions, if the SW can handle it.
140
141
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71403 if axi_m2s.write.aw.valid and axi_s2m.write.aw.ready then
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2147 if to_integer(unsigned(axi_m2s.write.aw.len)) /= len or to_integer(unsigned(axi_m2s.write.aw.size)) /= size then
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16 write_error <= true;
144 else
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2131 write_error <= false;
146 end if;
147 end if;
148
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71403 if axi_m2s.read.ar.valid and axi_s2m.read.ar.ready then
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2225 if to_integer(unsigned(axi_m2s.read.ar.len)) /= len or to_integer(unsigned(axi_m2s.read.ar.size)) /= size then
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8 read_error <= true;
152 else
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142824 read_error <= false;
154 end if;
155 end if;
156 end process;
157
158 end architecture;
159