tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_to_axi_lite_vec.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 48 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Convenience wrapper for splitting and CDC'ing a register bus.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library common;
15 use common.addr_pkg.all;
16
17 library axi;
18 use axi.axi_pkg.all;
19 use axi.axi_lite_pkg.all;
20
21
22
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28376 entity axi_to_axi_lite_vec is
23 generic (
24 axi_lite_slaves : addr_and_mask_vec_t;
25 clocks_are_the_same : boolean_vector(axi_lite_slaves'range) := (others => true);
26 pipeline : boolean := false;
27 -- Only needed if pipeline is enabled
28 data_width : positive := 32
29 );
30 port (
31 clk_axi : in std_logic;
32 axi_m2s : in axi_m2s_t;
33 8 axi_s2m : out axi_s2m_t;
34 1608
35
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1096 -- Only need to set if different from axi_clk
36
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201 clk_axi_lite_vec : in std_logic_vector(axi_lite_slaves'range) := (others => '0');
37
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137 axi_lite_m2s_vec : out axi_lite_m2s_vec_t(axi_lite_slaves'range);
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80 axi_lite_s2m_vec : in axi_lite_s2m_vec_t(axi_lite_slaves'range)
39
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14881 );
40
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2561 end entity;
41 2968
42
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2896 architecture a of axi_to_axi_lite_vec is
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6416 signal axi_lite_m2s, axi_lite_pipelined_m2s : axi_lite_m2s_t := axi_lite_m2s_init;
45
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1648 signal axi_lite_s2m, axi_lite_pipelined_s2m : axi_lite_s2m_t := axi_lite_s2m_init;
46
47 8 constant addr_width : positive := addr_bits_needed(axi_lite_slaves);
48
49 begin
50
51 ------------------------------------------------------------------------------
52 8 axi_to_axi_lite_inst : entity work.axi_to_axi_lite
53 generic map (
54 data_width => 32
55 )
56 port map (
57 clk => clk_axi,
58
59 axi_m2s => axi_m2s,
60 axi_s2m => axi_s2m,
61
62 axi_lite_m2s => axi_lite_m2s,
63 axi_lite_s2m => axi_lite_s2m
64 );
65
66
67 ------------------------------------------------------------------------------
68 pipeline_gen : if pipeline generate
69
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1104 axi_lite_pipeline_inst : entity work.axi_lite_pipeline
70 generic map (
71 data_width => data_width,
72 addr_width => addr_width
73 )
74 port map (
75 clk => clk_axi,
76 --
77 master_m2s => axi_lite_m2s,
78 master_s2m => axi_lite_s2m,
79 --
80 slave_m2s => axi_lite_pipelined_m2s,
81 slave_s2m => axi_lite_pipelined_s2m
82 );
83
84 else generate
85
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223214 axi_lite_pipelined_m2s <= axi_lite_m2s;
86 axi_lite_s2m <= axi_lite_pipelined_s2m;
87
88 end generate;
89
90 ------------------------------------------------------------------------------
91
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16 axi_lite_to_vec_inst : entity work.axi_lite_to_vec
92 generic map (
93 axi_lite_slaves => axi_lite_slaves,
94 clocks_are_the_same => clocks_are_the_same
95 )
96 port map (
97 clk_axi_lite => clk_axi,
98 axi_lite_m2s => axi_lite_pipelined_m2s,
99 axi_lite_s2m => axi_lite_pipelined_s2m,
100
101 clk_axi_lite_vec => clk_axi_lite_vec,
102 axi_lite_m2s_vec => axi_lite_m2s_vec,
103 axi_lite_s2m_vec => axi_lite_s2m_vec
104 );
105
106 end architecture;
107