tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_w_fifo.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 24 24 100.0%
Branches: 68 92 73.9%

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1 204 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- FIFO for AXI write data channel (W). Can be used as clock crossing by setting
9 -- the "asynchronous" generic.
10 -- -------------------------------------------------------------------------------------------------
11
12 library ieee;
13 use ieee.std_logic_1164.all;
14
15 library common;
16 use common.attribute_pkg.all;
17
18 library fifo;
19
20 use work.axi_pkg.all;
21
22
23
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52294 entity axi_w_fifo is
24 generic (
25 asynchronous : boolean;
26 data_width : positive;
27 depth : natural;
28 enable_packet_mode : boolean := false;
29 ram_type : ram_style_t := ram_style_auto
30 );
31 port (
32 clk : in std_logic;
33 --
34 input_m2s : in axi_m2s_w_t;
35 input_s2m : out axi_s2m_w_t := axi_s2m_w_init;
36 10 --
37 output_m2s : out axi_m2s_w_t := axi_m2s_w_init;
38 10 output_s2m : in axi_s2m_w_t;
39 10 -- Level of the FIFO. If this is an asynchronous FIFO, this value is on the "output" side.
40 output_level : out integer range 0 to depth := 0;
41 10
42 10 -- Only needs to assign the clock if generic asynchronous is "True"
43
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1120 clk_input : in std_logic := '0'
44 10 );
45 end entity;
46
47
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78 architecture a of axi_w_fifo is
48
49 10 begin
50
51 10 passthrough_or_fifo : if depth = 0 generate
52 4954574 output_m2s <= input_m2s;
53
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16440 input_s2m <= output_s2m;
54 10
55 else generate
56
57
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20 constant w_width : integer := axi_m2s_w_sz(data_width);
58
59 20 signal read_valid : std_logic := '0';
60 784 signal read_data, write_data : std_logic_vector(w_width - 1 downto 0);
61
62 10 begin
63
64 ------------------------------------------------------------------------------
65 4110 assign : process(all)
66 begin
67
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5919563 output_m2s <= to_axi_m2s_w(read_data, data_width);
68
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35027 output_m2s.valid <= read_valid;
69
70
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1331026 write_data <= to_slv(input_m2s, data_width);
71 end process;
72
73
74 ------------------------------------------------------------------------------
75
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44 fifo_wrapper_inst : entity fifo.fifo_wrapper
76 generic map (
77 use_asynchronous_fifo => asynchronous,
78 width => w_width,
79 depth => depth,
80 enable_last => enable_packet_mode,
81 enable_packet_mode => enable_packet_mode,
82 ram_type => ram_type
83 )
84 port map(
85 clk => clk,
86 clk_read => clk,
87 clk_write => clk_input,
88 --
89 read_ready => output_s2m.ready,
90 read_valid => read_valid,
91 read_data => read_data,
92 read_level => output_level,
93 --
94 write_ready => input_s2m.ready,
95 write_valid => input_m2s.valid,
96 write_data => write_data,
97 write_last => input_m2s.last
98 );
99
100 end generate;
101
102 end architecture;
103