tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/axi/axi_write_cdc.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Clock domain crossing for an AXI write bus.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13
14 library common;
15 use common.attribute_pkg.all;
16
17 library fifo;
18
19 use work.axi_pkg.all;
20
21
22
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7128 entity axi_write_cdc is
23 generic (
24 id_width : natural;
25 addr_width : positive;
26 data_width : positive;
27 enable_data_fifo_packet_mode : boolean;
28 address_fifo_depth : positive;
29 address_fifo_ram_type : ram_style_t := ram_style_auto;
30 data_fifo_depth : positive;
31 6 data_fifo_ram_type : ram_style_t := ram_style_auto;
32 12 response_fifo_depth : positive;
33 6 response_fifo_ram_type : ram_style_t := ram_style_auto
34
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1944 );
35 12 port (
36 6 clk_input : in std_logic;
37
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3402 input_m2s : in axi_write_m2s_t;
38 12 input_s2m : out axi_write_s2m_t := axi_write_s2m_init;
39 6 --
40
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12 clk_output : in std_logic;
41 output_m2s : out axi_write_m2s_t := axi_write_m2s_init;
42 output_s2m : in axi_write_s2m_t;
43 6 output_data_fifo_level : out integer range 0 to data_fifo_depth := 0
44 );
45 end entity;
46
47 12 architecture a of axi_write_cdc is
48
49 begin
50
51 ------------------------------------------------------------------------------
52
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6 axi_address_fifo_inst : entity work.axi_address_fifo
53 generic map (
54 id_width => id_width,
55 addr_width => addr_width,
56 asynchronous => true,
57 depth => address_fifo_depth,
58 ram_type => address_fifo_ram_type
59 )
60 port map (
61 clk => clk_output,
62 --
63 input_m2s => input_m2s.aw,
64 input_s2m => input_s2m.aw,
65 --
66 output_m2s => output_m2s.aw,
67 output_s2m => output_s2m.aw,
68 --
69 clk_input => clk_input
70 );
71
72
73 ------------------------------------------------------------------------------
74
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6 axi_w_fifo_inst : entity work.axi_w_fifo
75 generic map (
76 data_width => data_width,
77 asynchronous => true,
78 enable_packet_mode => enable_data_fifo_packet_mode,
79 depth => data_fifo_depth,
80 ram_type => data_fifo_ram_type
81 )
82 port map (
83 clk => clk_output,
84 --
85 input_m2s => input_m2s.w,
86 input_s2m => input_s2m.w,
87 --
88 output_m2s => output_m2s.w,
89 output_s2m => output_s2m.w,
90 output_level => output_data_fifo_level,
91 --
92 clk_input => clk_input
93 );
94
95
96 ------------------------------------------------------------------------------
97
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12 axi_b_fifo_inst : entity work.axi_b_fifo
98 generic map (
99 id_width => id_width,
100 asynchronous => true,
101 depth => response_fifo_depth,
102 ram_type => response_fifo_ram_type
103 )
104 port map (
105 clk => clk_output,
106 --
107 input_m2s => input_m2s.b,
108 input_s2m => input_s2m.b,
109 --
110 output_m2s => output_m2s.b,
111 output_s2m => output_s2m.b,
112 --
113 clk_input => clk_input
114 );
115
116 end architecture;
117