tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/bfm/axi_write_slave.vhd
Date: 2021-07-25 04:08:32
Exec Total Coverage
Lines: 0 27 0.0%
Branches: 0 168 0.0%

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1 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Wrapper around VUnit BFM that uses convenient record types for the AXI signals.
9 -- -------------------------------------------------------------------------------------------------
10
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14
15 library vunit_lib;
16 context vunit_lib.vc_context;
17
18 library axi;
19 use axi.axi_pkg.all;
20
21
22 entity axi_write_slave is
23 generic (
24 axi_slave : axi_slave_t;
25 data_width : positive;
26 -- Note that the VUnit BFM creates and integer_vector_ptr of length 2**id_width, so a large
27 -- value for id_width might crash your simulator.
28 id_width : natural := 8;
29 w_fifo_depth : natural := 0
30 );
31 port (
32 clk : in std_logic;
33 axi_write_m2s : in axi_write_m2s_t := axi_write_m2s_init;
34 axi_write_s2m : out axi_write_s2m_t := axi_write_s2m_init
35 );
36 end entity;
37
38 architecture a of axi_write_slave is
39
40 signal w_fifo_m2s : axi_m2s_w_t := axi_m2s_w_init;
41 signal w_fifo_s2m : axi_s2m_w_t := axi_s2m_w_init;
42
43 signal awid, bid : std_logic_vector(id_width - 1 downto 0) := (others => '0');
44 signal awaddr : std_logic_vector(axi_write_m2s.aw.addr'range) := (others => '0');
45 signal awlen : std_logic_vector(axi_write_m2s.aw.len'range) := (others => '0');
46 signal awsize : std_logic_vector(axi_write_m2s.aw.size'range) := (others => '0');
47
48 begin
49
50 ------------------------------------------------------------------------------
51 -- Optionally use a FIFO for the data channel. This enables a data flow pattern where
52 -- the AXI slave can accept a lot of data (many bursts) before a single address transactions
53 -- occurs. This can affect the behavior of your AXI master, and is a case that needs to
54 -- tested sometimes.
55 axi_w_fifo_inst : entity axi.axi_w_fifo
56 generic map (
57 data_width => data_width,
58 asynchronous => false,
59 depth => w_fifo_depth
60 )
61 port map (
62 clk => clk,
63 --
64 input_m2s => axi_write_m2s.w,
65 input_s2m => axi_write_s2m.w,
66 --
67 output_m2s => w_fifo_m2s,
68 output_s2m => w_fifo_s2m
69 );
70
71
72 ------------------------------------------------------------------------------
73 axi_write_slave_inst : entity vunit_lib.axi_write_slave
74 generic map (
75 axi_slave => axi_slave
76 )
77 port map (
78 aclk => clk,
79
80 awvalid => axi_write_m2s.aw.valid,
81 awready => axi_write_s2m.aw.ready,
82 awid => awid,
83 awaddr => awaddr,
84 awlen => awlen,
85 awsize => awsize,
86 awburst => axi_write_m2s.aw.burst,
87
88 wvalid => w_fifo_m2s.valid,
89 wready => w_fifo_s2m.ready,
90 wdata => w_fifo_m2s.data(data_width - 1 downto 0),
91 wstrb => w_fifo_m2s.strb,
92 wlast => w_fifo_m2s.last,
93
94 bvalid => axi_write_s2m.b.valid,
95 bready => axi_write_m2s.b.ready,
96 bid => bid,
97 bresp => axi_write_s2m.b.resp
98 );
99
100 awid <= std_logic_vector(axi_write_m2s.aw.id(id_width - 1 downto 0));
101 awaddr <= std_logic_vector(axi_write_m2s.aw.addr);
102 awlen <= std_logic_vector(axi_write_m2s.aw.len);
103 awsize <= std_logic_vector(axi_write_m2s.aw.size);
104
105 axi_write_s2m.b.id(bid'range) <= unsigned(bid);
106
107 end architecture;
108