tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/block_design_mock.vhd
Date: 2021-07-26 04:08:16
Exec Total Coverage
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1 36 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11
12 library vunit_lib;
13 context vunit_lib.vunit_context;
14 context vunit_lib.vc_context;
15
16 library axi;
17 use axi.axi_pkg.all;
18
19 library bfm;
20
21 library reg_file;
22 use reg_file.reg_operations_pkg.all;
23
24 use work.top_level_sim_pkg.all;
25 use work.artyz7_top_pkg.all;
26
27
28
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13519 entity block_design_mock is
29 port (
30 clk_m_gp0 : in std_logic;
31
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1218 m_gp0_m2s : out axi_m2s_t;
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930 m_gp0_s2m : in axi_s2m_t;
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3234 clk_s_hp0 : in std_logic;
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162 s_hp0_m2s : in axi_m2s_t;
36 6 s_hp0_s2m : out axi_s2m_t;
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612 pl_clk0 : out std_logic := '0';
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1854 pl_clk1 : out std_logic := '0'
40 );
41
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1620 end entity;
42 318
43 architecture a of block_design_mock is
44
45 6 constant pl_clk0_period : time := 10 ns; -- 100 MHz
46 6 constant pl_clk1_period : time := 5 ns; -- 200 MHz
47
48 12 constant axi_read_slave, axi_write_slave : axi_slave_t := new_axi_slave(
49 address_fifo_depth => 1,
50 memory => axi_memory
51 );
52
53 begin
54
55 813 pl_clk0 <= not pl_clk0 after pl_clk0_period / 2;
56 542 pl_clk1 <= not pl_clk1 after pl_clk1_period / 2;
57
58
59 ------------------------------------------------------------------------------
60 -- If our register AXI master port used different dimensions than these
61 -- we would need to create another bus master, probably in top_level_sim_pkg.
62
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12 assert m_gp0_data_width = data_length(regs_bus_master);
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12 assert m_gp0_addr_width = address_length(regs_bus_master);
64
65 6 axi_master_inst : entity bfm.axi_master
66 generic map (
67 bus_handle => regs_bus_master
68 )
69 port map (
70 clk => clk_m_gp0,
71
72 axi_read_m2s => m_gp0_m2s.read,
73 axi_read_s2m => m_gp0_s2m.read,
74
75 axi_write_m2s => m_gp0_m2s.write,
76 axi_write_s2m => m_gp0_s2m.write
77 );
78
79
80 ------------------------------------------------------------------------------
81 12 axi_slave_inst : entity bfm.axi_slave
82 generic map (
83 axi_read_slave => axi_read_slave,
84 axi_write_slave => axi_write_slave,
85 data_width => 64
86 )
87 port map (
88 clk => clk_s_hp0,
89
90 axi_read_m2s => s_hp0_m2s.read,
91 axi_read_s2m => s_hp0_s2m.read,
92
93 axi_write_m2s => s_hp0_m2s.write,
94 axi_write_s2m => s_hp0_s2m.write
95 );
96
97 end architecture;
98