tsfpga VHDL coverage


Directory: generated/vunit_out/preprocessed/
File: generated/vunit_out/preprocessed/artyz7/block_design_pkg.vhd
Date: 2021-07-26 04:08:16
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6 -- -------------------------------------------------------------------------------------------------
2 -- Copyright (c) Lukas Vik. All rights reserved.
3 --
4 -- This file is part of the tsfpga project.
5 -- https://tsfpga.com
6 -- https://gitlab.com/tsfpga/tsfpga
7 -- -------------------------------------------------------------------------------------------------
8 -- Component generated from Vivado:
9 -- Go to IP sources, right click your block design and select "Create HDL wrapper".
10 -- Choose "Copy..." in the popup.
11 -- -------------------------------------------------------------------------------------------------
12
13 library ieee;
14 use ieee.std_logic_1164.all;
15
16
17 package block_design_pkg is
18
19 component block_design is
20 port (
21 M_AXI_GP0_arvalid : out STD_LOGIC;
22 M_AXI_GP0_awvalid : out STD_LOGIC;
23 M_AXI_GP0_bready : out STD_LOGIC;
24 M_AXI_GP0_rready : out STD_LOGIC;
25 M_AXI_GP0_wlast : out STD_LOGIC;
26 M_AXI_GP0_wvalid : out STD_LOGIC;
27 M_AXI_GP0_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
28 M_AXI_GP0_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
29 M_AXI_GP0_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
30 M_AXI_GP0_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
31 M_AXI_GP0_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
32 M_AXI_GP0_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
33 M_AXI_GP0_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
34 M_AXI_GP0_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
35 M_AXI_GP0_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
36 M_AXI_GP0_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
37 M_AXI_GP0_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
38 M_AXI_GP0_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
39 M_AXI_GP0_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
40 M_AXI_GP0_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
41 M_AXI_GP0_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
42 M_AXI_GP0_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
43 M_AXI_GP0_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
44 M_AXI_GP0_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
45 M_AXI_GP0_awlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
46 M_AXI_GP0_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
47 M_AXI_GP0_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
48 M_AXI_GP0_arready : in STD_LOGIC;
49 M_AXI_GP0_awready : in STD_LOGIC;
50 M_AXI_GP0_bvalid : in STD_LOGIC;
51 M_AXI_GP0_rlast : in STD_LOGIC;
52 M_AXI_GP0_rvalid : in STD_LOGIC;
53 M_AXI_GP0_wready : in STD_LOGIC;
54 M_AXI_GP0_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
55 M_AXI_GP0_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
56 M_AXI_GP0_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
57 M_AXI_GP0_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
58 M_AXI_GP0_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
59 S_AXI_HP0_arready : out STD_LOGIC;
60 S_AXI_HP0_awready : out STD_LOGIC;
61 S_AXI_HP0_bvalid : out STD_LOGIC;
62 S_AXI_HP0_rlast : out STD_LOGIC;
63 S_AXI_HP0_rvalid : out STD_LOGIC;
64 S_AXI_HP0_wready : out STD_LOGIC;
65 S_AXI_HP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
66 S_AXI_HP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
67 S_AXI_HP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 );
68 S_AXI_HP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 );
69 S_AXI_HP0_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
70 S_AXI_HP0_arvalid : in STD_LOGIC;
71 S_AXI_HP0_awvalid : in STD_LOGIC;
72 S_AXI_HP0_bready : in STD_LOGIC;
73 S_AXI_HP0_rready : in STD_LOGIC;
74 S_AXI_HP0_wlast : in STD_LOGIC;
75 S_AXI_HP0_wvalid : in STD_LOGIC;
76 S_AXI_HP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
77 S_AXI_HP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
78 S_AXI_HP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
79 S_AXI_HP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
80 S_AXI_HP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
81 S_AXI_HP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
82 S_AXI_HP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
83 S_AXI_HP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
84 S_AXI_HP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
85 S_AXI_HP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
86 S_AXI_HP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
87 S_AXI_HP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
88 S_AXI_HP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
89 S_AXI_HP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
90 S_AXI_HP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
91 S_AXI_HP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
92 S_AXI_HP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 );
93 S_AXI_HP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 );
94 S_AXI_HP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 );
95 S_AXI_HP0_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
96 S_AXI_HP0_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
97 M_AXI_GP0_ACLK : in STD_LOGIC;
98 FCLK_CLK0 : out STD_LOGIC;
99 S_AXI_HP0_ACLK : in STD_LOGIC;
100 FCLK_CLK1 : out STD_LOGIC
101 );
102 end component block_design;
103
104 end package;
105